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參數(shù)資料
| 型號： | PCI2050PDV |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050PDV |
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical data (continued)
66-MHz PCI signal timing specifications
Figure 2 illustrates the PCI signal timing specification.
NOTE: Vtest
–
1.5 V for 5-V signals; 0.4 VCC for 3.3-V signals
ton
th
Valid
Valid
Vtest
tv
tsu
CLK
Output
Input
Figure 2. PCI Signal Timing Measurement Conditions
66-MHz PCI signal timing
PARAMETER
MIN
MAX
UNIT
tv(bus)
tv(ptp)
ton
toff
tsu(bus)
tsu(ptp)
th
NOTES:
CLK to signal valid delay - bused signals (see Notes 1, 2, and 3)
2
6
ns
CLK to signal valid delay
–
point to point (see Notes 1, 2, and 3)
2
6
ns
Float to active delay (see Notes 1, 2, and 3)
2
ns
Active to float delay (see Notes 1, 2, and 3)
14
ns
Input setup time to CLK
–
bused signal (see Notes 1, 2, and 3)
3
ns
Input setup time to CLK
–
point-to-point (see Notes 1, 2, and 3)
5
ns
Input signal hold time from CLK (see Notes 1 and 2)
0
ns
1. See Figure 2
2. All primary interface signals are synchronized to P_CLK and all secondary interface signals are synchronized to S_CLK.
3. Bused signals are as follows:
P_AD, P_C/BE, P_PAR, P_PERR, P_SERR, P_FRAME, P_IRDY, P_TRDY, P_LOCK, P_DEVSEL, P_STOP, P_IDSEL, S_AD,
S_C/BE, S_PAR, S_PERR, S_SERR, S_FRAME, S_IRDY, S_TRDY, S_LOCK, S_DEVSEL, S_STOP
Point-to-point signals are as follows:
P_REQ, S_REQx, P_GNT, S_GNTx
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