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參數(shù)資料
| 型號： | PCI2050PDV |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050PDV |
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical data
66-MHz PCI clock signal ac parameters
The ac specification consists of input requirements and output responses. The input requirements consists of
setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal.
The ac specifications are defined are separately for each clock domain within the PCI2050A.
Figure 1 shows the ac parameters measurements for P_CLK and S_CLK signals.
NOTE: Vt(1)
–
2.0 V for 5-V clocks; 0.5 VCC for 3.3-V clocks
Vt(2)
–
1.5 V for 5-V clocks; 0.4 VCC for 3.3-V clocks
Vt(3)
–
0.8 V for 5-V clocks; 0.3 VCC for 3.3-V clocks
th
tc
tl
th
tl
tr
tr
tc
tr
tr
ts
ts
Vt(1)
Vt(2)
Vt(3)
Vt(1)
Vt(2)
Vt(3)
P_CLK
S_CLK
Figure 1. PCI Clock Signal AC Parameter Measurements
66 MHz PCI clock signal ac parameters
PARAMETER
MIN
MAX
UNIT
tc
t(h)
t(l)
t(PSS)
td(SCLK)
tr(SCLK)
tf(SCLK)
td(skew)
tsk
P_CLK, S_CLK cycle time
15
30
ns
P_CLK, S_CLK high time
6
ns
P_CLK, S_CLK low time
6
ns
P_CLK, S_CLK slew rate (0.2 Vcc to 0.6 Vcc)
1.5
4
V/ns
Delay from P_CLK to S_CLK
0
7
ns
P_CLK rising to S_CLK rising
0
7
ns
P_CLK falling to S_CLK falling
0
7
ns
S_CLK0 duty cycle skew from P_CLK duty cycle
0.750
ns
S_CLKx to SCLKy
0.500
ns
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