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參數(shù)資料
| 型號： | PCI2050PDV |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050PDV |
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
bridge configuration header (continued)
secondary status register
The bit 5 in the status register is hardwired to 0 in PCI2050. However, in PCI2050A it indicates whether the
primary PCI interface is 66-MHz capable.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Secondary Status
Type
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Secondary Status
Read-only, read/write (see individual bit descriptions)
IEh
0200
Table 3. Status Register
BIT
TYPE
FUNCTION
15-6
Same as
PCI2050
Same as PCI2050.
5
R
66-MHz capable. Bit 5 indicates whether the primary interface is 66-MHz capable. It reads as 0 when CONFIG66 is tied
low to indicate that PCI2050A is not 66 MHz capable and reads as 1 when CONFIG66 is tied high to indicate that the
primary bus is 66-MHz capable.
4-0
Same as
PCI2050
Same as PCI2050.
extension registers
The extension registers for PCI2050A are exactly the same as the extension registers for PCI2050 except for
the following registers.
diagnostics register
The register is used to enable or disable posted write combing of PCI2050A.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
TI Diagnostics
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
TI Diagnostics
Read-only, read/write (see individual bit descriptions)
F0h
0000h
Table 4. TI Diagnostics Register
BIT
TYPE
FUNCTION
15-6
R
Reserved. Bit 15
–
1 return 0s when read.
0
R/W
Disable posted write combining.
0: Enable posted write combining (Default)
1: Disable posted write combining
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