參數(shù)資料
型號(hào): PCA9549
廠商: NXP Semiconductors N.V.
英文描述: Octal bus switch with individually I2C-bus controlled enables
中文描述: 個(gè)別八路與I2C總線開關(guān),總線控制,使
文件頁數(shù): 8/24頁
文件大?。?/td> 126K
代理商: PCA9549
PCA9549_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 11 July 2006
8 of 24
Philips Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
7.
Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Figure 8
).
7.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Figure 9
).
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Figure 10
).
Fig 8.
Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9.
Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
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