參數(shù)資料
型號(hào): PCA9549
廠商: NXP Semiconductors N.V.
英文描述: Octal bus switch with individually I2C-bus controlled enables
中文描述: 個(gè)別八路與I2C總線開(kāi)關(guān),總線控制,使
文件頁(yè)數(shù): 6/24頁(yè)
文件大?。?/td> 126K
代理商: PCA9549
PCA9549_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 11 July 2006
6 of 24
Philips Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
[1]
Several bits can be enabled at the same time. For example, B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1,
B1 = 0, B0 = 0, means that bit 8, bit 6, bit 5, bit 2, and bit 1 are disabled and bit 7, bit 4, and bit 3 are
enabled.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t
w(rst)L
, the PCA9549 will reset its
registers and I
2
C-bus state machine and will open all bits. The RESET input must be
connected to V
DD
through a pull-up resistor.
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9549 in
a reset state until V
DD
has reached V
POR
. At this point, the reset condition is released and
the PCA9549 registers and I
2
C-bus state machine are initialized to their default states, all
zeroes causing all the bits to be open (high-impedance state).
6.5 CBT characteristic over V
DD
range
The bus switch is optimized at 5.0 V but can operate over the entire supply range with
lower V
o(sw)
voltage and higher gate resistance.
Table 4.
Write = channel selection; read = channel status.
B7
B6
B5
Control register
B4
B3
B2
B1
B0
0
1
Command
bit 1 disabled
bit 1 enabled
bit 2 disabled
bit 2 enabled
bit 3 disabled
bit 3 enabled
bit 4 disabled
bit 4 enabled
bit 5 disabled
bit 5 enabled
bit 6 disabled
bit 6 enabled
bit 7 disabled
bit 7 enabled
bit 8 disabled
bit 8 enabled
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
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