參數(shù)資料
型號: PCA9549
廠商: NXP Semiconductors N.V.
英文描述: Octal bus switch with individually I2C-bus controlled enables
中文描述: 個別八路與I2C總線開關(guān),總線控制,使
文件頁數(shù): 13/24頁
文件大?。?/td> 126K
代理商: PCA9549
PCA9549_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 11 July 2006
13 of 24
Philips Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
10. Dynamic characteristics
[1]
Pass gate propagation delay is calculated from the 6
typical R
on
and the 50 pF load capacitance.
After this period, the first clock pulse is generated.
[2]
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4]
C
b
= total capacitance of one bus line in pF.
Table 8.
Symbol
Dynamic characteristics
Parameter
Conditions
Standard-mode
I
2
C-bus
Min
-
Fast-mode I
2
C-bus
Unit
Max
0.25
[1]
Min
Max
0.25
[1]
t
PD
propagation delay
A to B;
V
DD
= 4.5 V to 5.5 V
-
ns
f
SCL
t
BUF
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL
signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
data valid time
0
4.7
100
-
0
1.3
400
-
kHz
μ
s
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
[2]
4.0
-
-
-
-
0.6
1.3
0.6
0.6
-
-
-
-
μ
s
μ
s
μ
s
μ
s
4.7
4.0
4.7
t
SU;STO
t
HD;DAT
t
SU;DAT
t
r
4.0
0
[3]
250
-
-
3.45
-
1000
0.6
0
[3]
100
20 + 0.1C
b
[4]
300
-
0.9
-
μ
s
μ
s
ns
ns
t
f
C
b
t
SP
-
-
-
300
400
50
20 + 0.1C
b
[4]
300
-
-
μ
s
μ
s
ns
400
50
t
VD;DAT
HIGH-to-LOW
LOW-to-HIGH
-
-
-
1
0.6
1
-
-
-
1
0.6
1
μ
s
μ
s
μ
s
t
VD;ACK
RESET
t
w(rst)L
t
rst
t
REC;STA
data valid acknowledge time
LOW-level reset time
reset time
recovery time to START condition
4
500
0
-
-
-
4
500
0
-
-
-
ns
ns
ns
SDA clear
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