參數(shù)資料
型號: PCA9506
廠商: NXP Semiconductors N.V.
英文描述: 40-bit I2C-bus I/O port with RESET, OE, and INT
中文描述: 40位I2C總線的I / O端口復(fù)位,光電,和INT
文件頁數(shù): 12/30頁
文件大?。?/td> 145K
代理商: PCA9506
9397 750 14939
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 February 2006
12 of 30
Philips Semiconductors
PCA9506
40-bit I
2
C-bus I/O port with RESET, OE, and INT
7.3.4
IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins.
Cx[y] = 0: The corresponding port pin is an output.
Cx[y] = 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.3.5
MSK0 to MSK4 - Mask interrupt registers
These registers mask the interrupt due to a change in the I/O pins configured as inputs. ‘x’
refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9506 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9506 registers and I
2
C-bus state machine will initialize to their default states.
Thereafter, V
DD
must be lowered below 0.2 V to reset the device.
7.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
w(rst)
. The
PCA9506 registers and I
2
C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
Table 7:
Legend: * default value.
Address
18h
19h
1Ah
1Bh
1Ch
IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Register
IOC0
IOC1
IOC2
IOC3
IOC4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
C0[7:0]
C1[7:0]
C2[7:0]
C3[7:0]
C4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
1111 1111*
1111 1111*
1111 1111*
1111 1111*
1111 1111*
Description
I/O Configuration register bank 0
I/O Configuration register bank 1
I/O Configuration register bank 2
I/O Configuration register bank 3
I/O Configuration register bank 4
Table 8:
Legend: * default value.
Address
20h
21h
22h
23h
24h
MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Register
MSK0
MSK1
MSK2
MSK3
MSK4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
M0[7:0]
M1[7:0]
M2[7:0]
M3[7:0]
M4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
1111 1111*
1111 1111*
1111 1111*
1111 1111*
1111 1111*
Description
Mask Interrupt register bank 0
Mask Interrupt register bank 1
Mask Interrupt register bank 2
Mask Interrupt register bank 3
Mask Interrupt register bank 4
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