參數(shù)資料
型號： PCA9506
廠商： NXP Semiconductors N.V.
英文描述： 40-bit I2C-bus I/O port with RESET, OE, and INT
中文描述： 40位I2C總線的I / O端口復(fù)位，光電，和INT
文件頁數(shù)： 11/30頁
文件大?。?/td> 145K
代理商： PCA9506
9397 750 14939
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 February 2006
11 of 30
Philips Semiconductors
PCA9506
40-bit I
2
C-bus I/O port with RESET, OE, and INT
7.3.2
OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection,
not
the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.3.3
PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 5:
Legend: * default value.
Address
08h
09h
0Ah
0Bh
0Ch
OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Register
OP0
OP1
OP2
OP3
OP4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
O0[7:0]
O1[7:0]
O2[7:0]
O3[7:0]
O4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
Description
Output Port register bank 0
Output Port register bank 1
Output Port register bank 2
Output Port register bank 3
Output Port register bank 4
Table 6:
Legend: * default value.
Address
10h
11h
12h
13h
14h
PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Register
PI0
PI1
PI2
PI3
PI4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
Description
Polarity Inversion register bank 0
Polarity Inversion register bank 1
Polarity Inversion register bank 2
Polarity Inversion register bank 3
Polarity Inversion register bank 4
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