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參數(shù)資料
| 型號(hào)： | PCA8802U/2AA/1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA8 |
| 封裝： | 1.19 X 1.14 MM, 0.22 MM HEIGHT, LEAD FREE, WLCSP-8 |
| 文件頁數(shù)： | 2/34頁 |
| 文件大小： | 160K |
| 代理商： | PCA8802U/2AA/1 |
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PCA8802_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 19 February 2009
10 of 34
NXP Semiconductors
PCA8802
Smartcard RTC
9.5.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal. Bit transfer is shown in Figure 13.
9.5.3 Bit order
Data is transferred MSB rst.
9.5.4 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is dened as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP
condition (P). The START and STOP conditions are shown in Figure 15.
The data on SDA is sampled with the rising edge of SCL. Data is output to SDA on the
falling edge of SCL.
9.5.5 System conguration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the device which is
controlled by the master is the slave.
Fig 13. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 14. Bit transfer
001aaj212
MSB
b7
b6
b5
b4
b3
b2
b1
b0
LSB
Fig 15. Denition of START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
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