參數(shù)資料
型號(hào)： PC33899CVW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： BRUSH DC MOTOR CONTROLLER, PDSO30
封裝： ROHS COMPLIANT, HSOP-30
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 990K
代理商： PC33899CVW
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
33899
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 13. OFF-State Fault Detection Diagram
In the full or half H-Bridge mode an open, short to ignition,
or short to GND latches the appropriate SPI fault bits until the
FLTCLR bit is set. Any additional faults that occur prior to
setting FLTCLR will be ignored.
Fault Detection During OFF State
Fault detection for both the high side and low side outputs
is done during the OFF state, when either the EN1 or EN2 pin
is a logic [1], by analyzing the states of both the high side and
low side outputs interacting to the external load. S1 is pulled
up internally via a high-impedance pull-up to VCC, while S0 is
pulled down internally to ground. In a normal load state, the
low-impedance (relative to the internal pull-ups/pull-downs)
will force both load connections to about 0.5 VCC. S1 is
compared with an internal reference of 0.75 VCC nominally,
while S0 is compared to an internal reference of 0.25VCC
nominally. Table 7 indicates what status the load will be in
based on the combination of the outputs of these two
comparators.
Once any of the above faults are indicated for a period of
time exceeding the OFF-state fault timer, the fault bit will be
latched into the SPI Fault register. The OFF-state fault timer
is started when either the EN1 or EN2 pin transitions from a
logic [1] to a logic [0] (both inputs previously logic [1]) or from
a logic [0] to a logic [1] (both inputs previously logic [0]). The
OFF-state filter time is substantially longer than the ON-state
to allow energy in the load to dissipate. False open state
faults may be set when the outputs are shut down and the
load current (reverse polarity only) takes more than the OFF-
state filter time to decay to zero. The microprocessor should
clear the open state fault SPI bit and read the Fault register
again under this condition.
0.75 VCC
EN2
0.25 VCC
S0
S1
VCC
OF
SGFON
SBFON
Fault
Timer
SGF
SBF
EN1
12 k
Ω
12 k
Ω
Note SGFON and SBFON are ON-State Fault.
Table 7. OFF-State Fault Detection
S1
S0
Load Status
<0.75 VCC
>0.25 VCC
Normal Load
<0.75 VCC
<0.25 VCC
Short to Ground
>0.75 VCC
<0.25 VCC
Open Load
>0.75 VCC
>0.25 VCC
Short to VIGNP
Load Current
(Reverse Polarity)
S0/S1 are at 2.5VDC,
No SPI Bits Set
Wake Up, Open
Fault Timer Starts
Open Fault
Timer Starts
Current in Load < 0, Erroneous
Open Fault SPI Bit Set
Goo Back
to Sleep
tFDO
S0
S1
EN1
EN2
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