參數(shù)資料
型號： P95020ZLLGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 65/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLGI
P95020 / Preliminary Datasheet
Revision 0.7.10
33
2010 Integrated Device Technology, Inc.
IC Address = Page-2: 26(0x1A), C Address = 0xA21A
IC Address = Page-2: 27(0x1B), C Address = 0xA21B
IC Address = Page-2: 37(0x25), C Address = 0xA225
IC Address = Page-2: 47(0x2F), C Address = 0xA22F
IC Address = Page-2: 49(0x31), C Address = 0xA231
thru Page-2: 53(0x35), C Address = 0xA235
IC Address = Page-2: 64(0x40), C Address = 0xA240
thru Page-2: 255(0xFF), C Address = 0xA2FF
2.13.2 AUDIO CLASS_D
– ID HI & LO Registers
This 24 bit read-only register contains a unique ID for each block.
ID_HI: IC Address = Page-2: 16(0x10), C Address = 0xA210
ID_LO: IC Address = Page-2: 17(0x11), C Address = 0xA211
Bit
Bit Name
Default
Setting
User
Type
Value
Description / Comments
[15:0]
ID
4D52h
R
Unique identifier
2.13.3 AUDIO CLASS_D
– VERSION HI & LO Registers
This 24 bit read-only register contains a unique version identifier for each block.
VERSION_HI: IC Address = Page-2: 18(0x12), C Address = 0xA212
VERSION_LO: IC Address = Page-2: 19(0x13), C Address = 0xA213
Bit
Bit Name
Default
Setting
User
Type
Value
Description / Comments
[15:0]
VERSION
0100h
R
Bits[15:8] updated on major RTL code change.
Bits[7:4] updated on minor RTL code change.
Bits[3:0] updated on metal layer bug fix.
2.13.4 AUDIO CLASS_D
– STATUS Registers
These are read-only status registers which provide feedback on the operation of the DSP Filtering functions
STATUS0: IC Address = Page-2: 20(0x14), C Address = 0xA214
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
[3:0]
fs_clk_synced_loss_cnt
0
0h
R
Count of the number of times synchronization to i_den is lost since
last initialize.
[6:4]
den_jitter
000b
R
latched max value of i_den jitter detected after fs_clk_synced.
Cleared on initialize. How many fclks is i_den for ch0 jittering
between samples.
7
fs_clk_synced
0b
R
1 = Input sample rate (i_den for ch0) is properly locked to fclk (within
tolerance).
STATUS1: IC Address = Page-2: 21(0x15), C Address = 0xA215
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
[7:0]
fclks_per_ch0_in_
sample
00h
R
Multiply this value by 32 to get the number of fclks between each ch0
input data sample. Knowing the fclk frequency you can then
determine sample rate. Also useful in making sure there are enough
fclks to allow the DSP filtering processes to complete before the next
input sample.
STATUS2: IC Address = Page-2: 22(0x16), C Address = 0xA216
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
0
zerodet_flag
0b
R
set when input zero detect of long string of zeros.
1
limit1
0b
R
1 = set if regz saturation after gain multiply for ch0. May change on a
sample by sample basis.
2
limit1
0b
R
1 = set if regz saturation after gain multiply for ch0. May change on a
sample by sample basis.
[5:3]
RESERVED
000b
R
RESERVED
6
limit0latch
0b
R
Latched version of limit0, clear via GAINCTRL[7].
7
limit1latch
0b
R
Latched version of limit1, clear via GAINCTRL[7].
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