參數(shù)資料
型號： P95020ZLLGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 127/137頁
文件大小： 3533K
代理商： P95020ZLLGI
P95020 / Preliminary Datasheet
Revision 0.7.10
9
2010 Integrated Device Technology, Inc.
PIN FUNCTIONS BY PIN NUMBER
Table 1
– LLG124 Pin Functions by Pin Number (See Figure 2)
MODULE
PIN #
PIN NAME
DESCRIPTION
I/O TYPE
GPIO_TSC
1
GPIO5/INT_OUT
GPIO 5: General Purpose I/O # 5
GPIO
(See Pins
INT_OUT : Interrupt Output
117-124
2
GPIO6/ADC1
GPIO 6: General Purpose I/O # 6
GPIO
also)
ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch-screen
3
GPIO7/ADC3
GPIO 7: General Purpose I/O # 7
GPIO
ADC3 : Auxiliary Input Channel 4 / Y- pin to 4-wire resistive touch-screen
4
GPIO8/ADC2
GPIO 8: General Purpose I/O # 8
GPIO
ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch-screen
5
GPIO9/ADC0/MCLK_IN
GPIO 9: General Purpose I/O # 9
GPIO
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch-screen
MCLK_IN : Master Clock Input
6
GPIO10
GPIO 10: General Purpose I/O # 10
GPIO
AUDIO
7
MIC_R-
MIC_R-: Analog Microphone Differential Stereo Right Inverting Input
A-I
8
MIC_R+/DMICDAT2
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input
A-I
DMICDAT2: Digital Microphone 2 Data Input
D-I
9
MICBIAS_R/DMICSEL
MICBIAS : Microphone Right Bias
A-O
DMICSEL : Digital Microphone Select (Common to both inputs)
D-O
10
MICBIAS_L/DMICCLK
MICBIAS : Microphone Left Bias
A-O
DMICCLK : Digital Microphone Clock (Common to both inputs)
D-O
11
MIC_L+/DMICDAT1
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input
A-I
DMICDAT1 : Digital Microphone 1 Data Input
D-I
12
MIC_L-
MIC_L- : Analog Microphone Differential Stereo Left Inverting Input
A-I
13
AFILT2
Microphone ADC Anti-Aliasing Filter Capacitor #2
A-I
14
AFILT1
Microphone ADC Anti-Aliasing Filter Capacitor #1
A-I
15
AGND_MIC
Microphone Ground (Analog Ground)
GND
16
LISLP
Line Input Stereo Left Non-Inverting
A-I
17
LISLM
Line Input Stereo Left Inverting
A-I
18
LISRP
Line Input Stereo Right Non-Inverting
A-I
19
LISRM
Line Input Stereo Right Inverting
A-I
20
LLO_L
Line Level Output, Left
A-O
21
LLO_R
Line Level Output, Right
A-O
22
AVREF
Analog Reference
A-O
23
VDD_AUDIO33
Filter Capacitor for Internal 3.3V AUDIO LDO
A-O
24
ADC_REF
ADC Reference Bypass Capacitor
A-I
25
HP_R
Right Headphone Output
A-O
26
HP_L
Left Headphone Output
A-O
27
AGND
Line Out Ground (Analog Ground)
GND
28
VIRT_GND
Virtual Ground for Cap-Less Output
A-O
LDO
29
LDO_GND
LDO Ground
GND
30
LDO_IN3
Input Voltage to LDOs for AUDIO Power (VDD_AUDIO33 &
VDD_AUDIO18)
AP-I
31
LDO_LP
Always on Low Power LDO Output
(Voltage Programmable to 3.0 V or 3.3 V)
AP-O
32
LDO_050_3
50mA LDO Output #3 (Voltage Range: 0.75-3.7 V)
AP-O
33
LDO_IN2
Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3
AP-I
34
LDO_050_2
50mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
AP-O
35
LDO_050_1
50mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
AP-O
36
LDO_050_0
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
I2CS.
AP-O
37
LDO_150_2
150mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
AP-O
38
LDO_IN1
Input Voltage to LDO_150_0, LDO_150_1, & LDO_050_2
AP-I
39
LDO_150_1
150mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
AP-O
40
LDO_150_0
150mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
AP-O
CKGEN
41
32KHZ_OUT2
Buffered 32.768kHz Output #2
D-O
42
CKGEN_GND
PLL Analog Ground
GND
43
32KHZ_CLKIN/XTALIN
32KHZ_CLKIN: External 32.768kHz Clock Input;
A-I
XTALIN : Input Pin when used with an external crystal
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