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| 型號(hào)： | P95020ZLLGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁(yè)數(shù)： | 21/137頁(yè) |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZLLGI |
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P95020 / Preliminary Datasheet
Revision 0.7.10
117
2010 Integrated Device Technology, Inc.
0101010
Reg_addr
Data[reg_addr]
Data[reg_addr+1]
Data[reg_addr+n]
W
S
A
0101010
Data[reg_addr]
Data[reg_addr]+1
Data[reg_addr+n+
m]
R
S
A
Data[reg_addr+n+
1]
Data[reg_addr+n+
2]
Data[...]
A
0101010
Data[reg_addr]
Data[reg_addr]+1
Data[reg_addr+2]
W
S
A
Data[reg_addr]
Data[reg_addr+1]
A
N
A
N
S: Start
R:Read (1)
A:ACK
N:NAK
P
P:Stop
Sr: Repeat
Start
0101010
Data[reg_addr]
Data[reg_addr]+1
Data[reg_addr+k]
R
S
A
Data[reg_addr+3]
Data[reg_addr+4]
Data[...]
A
N P
Reg_addr
0101010
R
Sr
W:Write (0)
Legend:
A
Data[…]
A
Figure 32
– I
2C Read / Write Operation
15.3 INTERRUPT DISPATCHER
The interrupt dispatcher of the P95020 directs interrupts to the internal or external processor according to the INT_DIR
configuration stored in the ACCM Register. Please note that the configuration register is in the same address space of
other functional modules and hence can be accessed by internal and external processor. Interrupts mapped to the
internal processor are merged and dispatched to embedded microcontroller. Interrupts mapped to the external processor
are merged and dispatched to the external pin (INT_OUT). To ease the interrupt indexing of the external processor, two
interrupt index registers (one for internal and the other for external) are defined to reflect the status of different types of
interrupt status bits. Please note that the index register is just reflects the interrupt status of the various modules and
there are no real registers implemented. Therefore, clearing a particular interrupt status must be performed in the module
which generated the interrupt.
15.4 ACCESS ARBITER
Access request from IC slave and embedded processor will be arbitrated with strict high priority to IC. The access is split
to byte-perbyte basis.
15.5 DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the P95020 via the digital audio data serial interface, or audio
bus. The audio bus on this device is flexible, including left or right justified data options, support for IS protocols,
programmable data length options.
The audio bus of P95020 can be configured for left or right justified, IS slave modes of operation. These modes are all
MSB-first, with data width programmable as 16, 20, 24 bits.
The world clock (I2S_WS1 or I2S_WS2) is used to define the beginning of a frame. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequency. The bit clock (I2S_BCLK1 or
I2S_BCLK2) is used to clock in and out the digital audio data across the serial bus. Each port may be programmed for 8
kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.050 kHz, 24 kHz, 44.1 kHz, 48 kHz, 88.2 kHz or 96 kHz sample rate.
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