參數(shù)資料
型號: P89V660FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 77/90頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2433
935280829557
P89V660FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
79 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Fig 41. I2C-bus interface timing
002aab861
tHD;STA
trCL
trDA
tSU;STA
tLOW
tHIGH
tSU;DAT
tHD;DAT
tsuDAT1
SCL
(input/
output)
SDA
(input/
output)
START or repeated START condition
tfCL
0.7VCC
0.3VCC
tsuDAT2
tSU;STO
repeated START condition
STOP condition
START
condition
0.7VCC
0.3VCC
tfDA
tBUF
Table 75.
SPI interface timing
Symbol
Parameter
Conditions
Variable clock
fosc =18MHz
Unit
Min
Max
Min
Max
fSPI
SPI operating frequency
0
Tcy(clk) /4
0
10
MHz
TSPICYC
SPI cycle time
4Tcy(clk)
-
222
-
ns
tSPILEAD
SPI enable lead time
250
-
250
-
ns
tSPILAG
SPI enable lag time
250
-
250
-
ns
tSPICLKH
SPICLK HIGH time
2Tcy(clk)
-111
-
ns
tSPICLKL
SPICLK LOW time
2Tcy(clk)
-111
-
ns
tSPIDSU
SPI data set-up time
master or slave; see
100
-
100
-
ns
tSPIDH
SPI data hold time
master or slave; see
100
-
100
-
ns
tSPIA
SPI access time
0
80
0
80
ns
tSPIDIS
SPI disable time
0
160
-
160
ns
tSPIDV
SPI enable to output
data valid time
-111
-
111
ns
tSPIOH
SPI output data hold
time
0-
0
-
ns
tSPIR
SPI rise time
SPI outputs (SPICLK,
MOSI, MISO)
-
100
-
100
ns
SPI inputs (SPICLK,
MOSI, MISO, SS)
-
2000
-
2000
ns
tSPIF
SPI fall time
SPI outputs (SPICLK,
MOSI, MISO)
-
100
-
100
ns
SPI inputs (SPICLK,
MOSI, MISO, SS)
-
2000
-
2000
ns
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