參數(shù)資料
型號: P89V660FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 20/90頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2433
935280829557
P89V660FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
27 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Table 15.
I2C-bus control register (S1CON - address D8H) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Reset
x
000
00x
0
Table 16.
I2C-bus control register (S1CON - address D8H) bit description
Bit
Symbol
Description
7,1,0
CR2:0
SCL clock selection. See Table 17.
2
AA
The Assert Acknowledge Flag. When set to 1, an acknowledge (LOW-state to SDA) will be returned
during the acknowledge clock pulse on the SCL line on the following situations:
1. The ‘own slave address’ has been received.
2. The general call address has been received while the general call bit (GC) in S1ADR is set.
3. A data byte has been received while the I2C-bus interface is in the Master Receiver mode.
4. A data byte has been received while the I2C-bus interface is in the addressed Slave Receiver
mode.
When cleared to 0, an not acknowledge (HIGH-state to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
1. A data byte has been received while the I2C-bus interface is in the Master Receiver mode.
2. A data byte has been received while the I2C-bus interface is in the addressed Slave Receiver
mode.
3SI
I2C-bus Interrupt Flag. This bit is set when one of the 25 possible I2C-bus states is entered. When EA
bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set. Must be cleared by
software by writing 0 to this bit.
4
STO
STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the I2C-bus. When the bus
detects the STOP condition, it will clear STO bit automatically. In slave mode, setting this bit can
recover from an error condition. In this case, no STOP condition is transmitted to the bus. The
hardware behaves as if a STOP condition has been received and it switches to ‘not addressed’ Slave
Receiver mode. The STO flag is cleared by hardware automatically.
5
STA
Start Flag. STA = 1: I2C-bus enters master mode, checks the bus and generates a START condition if
the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and
generates a START condition after a delay of a half clock period of the internal clock generator. When
the I2C-bus interface is already in master mode and some data is transmitted or received, it transmits
a repeated START condition. STA may be set at any time, it may also be set when the I2C-bus
interface is in an addressed slave mode. STA = 0: no START condition or repeated START condition
will be generated.
6ENS1
I2C-bus Interface Enable. When set, enables the I2C-bus interface. When clear, the I2C-bus function is
disabled.
Table 17.
I2C-bus clock rates
CR2:0
Bit frequency at fosc
6-clock mode
12-clock mode
fosc divided by
6 MHz
12 MHZ
6 MHz
12 MHz
6X
12X
000
479423
47128
256
001
54
107
27
54
112
224
010
63
125
31
63
96
192
011
75
150
37
75
80
160
100
12.5
25
6.25
12.5
480
960
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