參數(shù)資料
型號(hào): P89V660FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 51/90頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2433
935280829557
P89V660FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
55 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
2
CPHA
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
1
SPR1
SPI Clock Rate Select bit 1. Along with SPR0 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See Table 42.
0
SPR0
SPI Clock Rate Select bit 0. Along with SPR1 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See Table 42.
Table 42.
SPCR - SPI control register (address D5H) clock rate selection
SPR1
SPR0
SPICLK = fosc divided by
6-clock mode
12-clock mode
00
2
4
01
8
16
10
32
64
11
64
128
Table 43.
SPSR - SPI status register (address AAH) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
SPIF
WCOL
-
Table 44.
SPSR - SPI status register (address AAH) bit description
Bit
Symbol
Description
7
SPIF
SPI interrupt flag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES3 = 1, an interrupt is then generated. This bit is
cleared by software.
6
WCOL
Write Collision Flag. Set if the SPI data register is written to during
data transfer. This bit is cleared by software.
5 to 0
-
Reserved for future use. Should be set to ‘0’ by user programs.
Fig 24. SPI transfer format with CPHA = 0
Table 41.
SPCR - SPI control register (address D5H) bit description …continued
Bit
Symbol
Description
002aaa529
SPICLK cycle #
(for reference)
SPICLK (CPOL = 0)
SPICLK (CPOL = 1)
MOSI
(from master)
MISO
(from slave)
SS (to slave)
12
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
MSB
6543
2
1
LSB
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