參數(shù)資料
型號(hào): P87C554
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: 80C51 8-bit microcontroller(80C51 8位微控制器)
中文描述: 80C51的8位微控制器(80C51的8位微控制器)
文件頁(yè)數(shù): 67/78頁(yè)
文件大?。?/td> 393K
代理商: P87C554
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller
16K/512 OTP/ROM/ROMless, 8 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O
1999 Apr 07
67
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
I
2
C Interface (Refer to Figure 56)
5
t
HD;STA
START condition hold time
t
LOW
SCL low time
t
HIGH
SCL high time
t
RC
SCL rise time
t
FC
SCL fall time
t
SU;DAT1
Data set-up time
t
SU;DAT2
SDA set-up time (before rep. START cond.)
t
SU;DAT3
SDA set-up time (before STOP cond.)
t
HD;DAT
Data hold time
t
SU;STA
Repeated START set-up time
t
SU;STO
STOP condition set-up time
t
BUF
Bus free time
t
RD
SDA rise time
t
FD
SDA fall time
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. t
CLCL
= 1/f
OSC
= one oscillator clock period at pin XTAL1. For 62ns (42s) < t
CLCL
< 285ns (16MHz (24Hz) > f
OSC
> 3.5MHz) the SI01
interface meets the I
2
C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
14 t
CLCL
16 t
CLCL
14 t
CLCL
1
μ
s
0.3
μ
s
250ns
250ns
250ns
0ns
14 t
CLCL
14 t
CLCL
14 t
CLCL
1
μ
s
0.3
μ
s
> 4.0
μ
s
1
> 4.7
μ
s
1
> 4.0
μ
s
1
2
< 0.3
μ
s
3
> 20 t
CLCL
– t
RD
> 1
μ
s
1
> 8 t
CLCL
> 8 t
CLCL
– t
FC
> 4.7
μ
s
1
> 4.0
μ
s
1
> 4.7
μ
s
1
2
< 0.3
μ
s
3
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