參數(shù)資料
型號： ORT82G5-1FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 64/119頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
49
Figure 31. Clocking for Eight Channel Alignment
Reset Operation
The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset,
or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to
approximately 80% of the nominal value of 1.5V. Following this event, the device will be ready for normal operation
after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES channels and resets all microprocessor and internal registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the
channel conguration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four
channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for nor-
mal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES
internal registers and counters. The microprocessor registers are not affected. It should also be noted that the
embedded block cannot be accessed until after FPGA conguration is complete.
FPGA
Logic
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
Common Logic, Quad B
Channel BA
Channel BB
Channel BD
Channel BC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RCK78B
TCK78B
RSYS_CLK_B1
TSYS_CLK_BA
RWCKBA
RWCKBB
TSYS_CLK_BB
RSYS_CLK_B2
RWCKBD
RWCKBC
TSYS_CLK_BC
TSYS_CLK_BD
TCK78A
2
REFCLK[P:N]_A
2
REFCLK[P:N]_B
156.25 MHz
All Clocks at
78.125 MHz
Eight Bidirectional
Channels of 3.125
Gbps Serial Data
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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