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| 型號(hào)： | ORT82G5-1FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 30/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
18
Figure 5. Transmit Path Timing - Single SERDES Channel
Each block also sends a clock to the FPGA logic. This clock, TCK78[A,B], is sourced from one of the four MUX
blocks and has the same frequency as TSYS_CLK_xx, but arbitrary phase. Within each MUX block, the low fre-
quency clock output is obtained by dividing by 4 the SERDES STBC311x clock which is used internally to synchro-
nize the transmit data words. TCKSEL control bits select the channel to source TCK78[A:B].
The internal signals STBDxx[9:0] (where xx is represents AA...BD or AC, AD, BC, BD) from the MUX block carry
unencoded character data and control bits. The 10th bit (STBDxx[9]) of each data lane into the SERDES is used to
force a negative disparity present state.
8b/10b Encoder and 1:10 Multiplexer
The 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. The input signals
to the block, STBDxx[7:0] are used for the 8-bit unencoded data. STBDxx[8] is used as the K_control input to indi-
cate whether the 8 data bits need to be encoded as special characters (K_control = 1) or as data characters
(K_control = 0). When STBDxx[9:0] = 1, a negative disparity present state is forced. When the encoder is bypassed
STBDxx[9:0] serve as the data bits for the 10-bit unencoded data.
Within the denition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission charac-
ters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to STBDxx[0], bit b to STBDxx[1], bit
c to STBDxx[2], bit d to STBDxx[3], bit e to STBDxx[4], bit i to STBDxx[5], bit f to STBDxx[6], bit g to STBDxx[7], bit
h to STBDxx[8], and bit j to STBDxx[9].
The 10-bit wide parallel data is converted to serial data by the 10:1 Multiplexer. The serial data are then sent to the
CML output buffer and are transmitted serially with STBDxx[0] transmitted rst and STBDxx[9] transmitted last.
CML Output Buffer
The transmitter’s CML output buffer is terminated on-chip in 86 ohms to optimize the data eye as well as to reduce
the number of discrete components required. The differential output swing reaches a maximum of 1.2 VPP in the
normal amplitude mode. A half amplitude mode can be selected via conguration register bit HAMP_xx. Half ampli-
tude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for
testing of the integrity (loss) of the physical medium.
A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi-
mize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted
over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for
FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result
of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes inter-
symbol interface which results in the closing of the data eye opening at the receiver.
.....
p
q
r
s
t
xyz
STBDxx[9:0]
.....
STBC311xx
.....
HDOUT_xx
p
4
p
5
p
6
p
7
p
8
p
9
p
0
p
1
p
2
p
3
LATENCY =
5 STBC311x CLOCKS
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| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
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| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
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| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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