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| 型號(hào)： | ORT82G5-1FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 50/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
36
For the ORT82G5, the SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS,and SYNC8_OOS signals can be used
with CH248_SYNC_xx to determine if the desired multi-channel alignment was successful. If, when
CH248_SYNC_xx goes high the corresponding OOS signal remains low, the data being transferred across the
core/FPGA interface is correctly aligned between channels. Note that only the signals corresponding to the
selected alignment mode will be meaningful.
For both devices, the code violation signals will only be valid if the corresponding CV_SELxx = 1. (If 8b10bR=0,
CV_SEL should also be zero. The CV_xx_OR signals are obtained by ORing four code violation signals from the
1:4 DEMUX block. These are primarily indicators of received signal quality since a single code violation will not
force a loss of sync (LOS) state in the word alignment state machines. Since these signals come from the DEMUX
block, if multi-channel alignment is enabled, the code violation signals correspond to data that must still be multi-
channel aligned. Hence these signals provide advance notication of detected violations in data that will appear at
the core/FPGA interface several clock cycles later. The exact number of clock cycles that the data is delayed
depends on the skew between the incoming data for the different channels.
Transceiver FPGA/Embedded Core Signals
Table 12 summarizes the interface signals between the FPGA logic and the core. In the table, an input refers to a
signal owing into the embedded core and an output refers to a signal owing out of the embedded core.
Table 11. Transceiver Embedded Core/FPGA Interface Signal Description for the ORT42G5
BA
29
CV_BA_OR
Code violation in one or more of the received 10-bit groups for channel BA
BA
19
SYNC2_B1_OOS
Dual channel synchronization of channels BA and BB not successful if 1
BB
29
CV_BB_OR
Code violation in one or more of the received 10-bit groups for channel BB
BB
19
SYNC4_B_OOS
Quad channel synchronization of SERDES quad B not successful if 1
BC
29
CV_BC_OR
Code violation in one or more of the received 10-bit groups for channel BC
BC
19
SYNC2_B2_OOS
Dual channel synchronization of channels BC and BD not successful if 1
BD
29
CV_BD_OR
Code violation in one or more of the received 10-bit groups for channel BD
BD
19
SYNC8_OOS
Eight channel synchronization not successful if 1
FPGA/Embedded Core
Interface Signal Name
(xx = [AC, AD, BC or BD])
Input (I) to or
Output (O)
from Core
Signal Description
Transmit Path Signals
TWDxx[31:0]
I
Transmit data – channel xx.
TCOMMAxx[3:0]
I
Transmit comma character – channel xx.
TBIT9xx[3:0]
I
Transmit force negative disparity – channel xx
TSYS_CLK_xx
I
Transmit low-speed clock to the FPGA – channel xx
TCK78[A:B]
O
Transmit low-speed clock to the FPGA – SERDES Quad [A:B].
Receive Path Signals
MRWDxx[39:0]
O
RWCKxx
O
Low-speed receive clock—Channel xx.
RCK78[A:B]
O
Receive low-speed clock to FPGA—SERDES Quad [A:B].
RSYS_CLK_A2
I
Low-speed receive FIFO clock for channels AC, AD
RSYS_CLK_B2
I
Low-speed receive FIFO clock for channels BC, BD
CV_SELxx
I
Enable detection of code violations in the incoming data
SYS_RST_N
I
Synchronous reset of the channel alignment blocks.
Table 10. Denition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5 (Continued)
Channel
Index
Bit Index
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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