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參數(shù)資料
| 型號(hào)： | ORT82G5-1FN680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 35/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
22
Receive CML Input Buffer and SERDES
The receiver section receives high-speed serial data at its differential CML input port. The receive input is an AC-
coupled input. The received data is sent to the clock recovery section which generates a recovered clock and
retimes the data. Valid data will be received after the receive PLL has locked to the input data frequency and phase.
The received serial data is converted to10-bit wide parallel data by the 1:10 demultiplexor. Clock recovery is per-
formed by the SERDES block for each of the eight receive channels. This recovered data is then aligned to a 10-bit
word boundary by detecting and aligning to a comma special character. Word alignment is done for either polarity
of the comma character. The 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of
data, a special character indicator bit and a SBYTSYNC_xx signal (where again xx is a placeholder for AA,...,BD or
AC, AD, BC, BD).
Data from a SERDES channel is sent to the DEMUX block in 10-bit raw form or 8-bit decoded form across the
SRBD_xx [9:0] port with a latency of approximately 14-23 cycles (bit periods of the incoming data). Accompanying
this data are the comma-character indicator (SBYTSYNC_xx), link-state indicator (SWDSYNC_xx), clocks
(SRBC0_xx, and SRBC1_xx), and code-violation indicator (SCVxx). The two internal clocks operated at twice the
reference clock frequency. Figure 7 shows the receive path timing for a single SERDES channel.
Figure 7. Receive Path Timing for a Single SERDES Channel
With the 8b10bR_xx control bit of the SERDES channel set to 1, the data presented at SRBD_xx[9:0] will be
decoded characters. Bit 8 will indicate whether SRBDxx[7:0] represents an ordinary data character (bit 8 = 0), or
whether SRBD_xx[7:0] represents a special character, like a comma. Bit 9 may be either a code violation indicator
or one of seven out of synchronization state indicators, as described later.
When 8b10bR is set to 0, the data at SRBD_xx[9:0] will not be decoded. The XAUI link-state machine should not
be used in this mode of operation. When in XAUI mode, the MUX/DEMUX looks for /A/ (as dened in IEEE 802.3ae
v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work
1:4 Demultiplexer (DEMUX)
The1:4 DEMUX has to accumulate four sets of characters presented to it at the SERDES receive interface and put
these out at one time at the low-speed receive interface.
Another task of the 1:4 DEMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the
synchronizing character leads off a new 4-byte word. In Fibre Channel mode, this synchronizing character is a
comma. This feature will be referred to as DEMUX word alignment in other areas of this document. DEMUX word
EMBEDDED CORE
.....
pq
r
s
t
x
y
z
SRBD_xx[9:0]
.....
SRBC0_xx
SRBC1_xx
.....
SBYTSYNC_xx,
SVCxx
q
0
r
8
r
9
s
0
p
4
p
5
p
6
p
7
p
8
p
9
.....
p
0
p
1
p
2
p
3
r
2
r
3
r
4
r
5
r
6
r
7
s
1
s
2
s
3
s
4
p
HDIN[P:N]_xx
SRBD_xx[9:0]
1-bit
10-bit
.....
LATENCY =
APPROX 23 CYCLES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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