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| 型號： | ORSO82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 89/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
40
frame (or A1A2 framing bytes). This frame pulse is used to synchronize multiple channels within an alignment
group.
If a channel is not in any alignment group, the FIFO control logic will set the FIFO-write-address to the beginning of
the FIFO, and will set the FIFO-read-address to the middle of the FIFO at the rst assertion of frame pulse after
reset or after the resync command.
The RX_FIFO_MIN register bits can be used to control the threshold for minimum unused buffer space in the align-
ment FIFOs between read and write pointers before OVFL status is agged. The synchronization algorithm con-
sists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when a frame pulse
from any channel within an alignment group has been received. The OOS alarm indicates the FIFO is out-of sync
and the channel skew exceeds that which can be handled by the FIFO. Once the frame pulse for all channels within
the alignment group have been received, the count is decremented by 2 until 0 is reached. Data are then read from
the FIFOs and output to the SPE generator before being sent to the FPGA.
For every alignment group, there is an OVFL and OOS status register bit. The OOS bit is agged when the down
counter in the synchronization algorithm has reached a value of 0 and frame pulse from all channels within an
alignment group have not been received. The OVFL bit is agged when the read address at the time of receiving a
frame pulse, is less than the minimum threshold set by RX_FIFO_MIN. In the memory map section OOS is referred
to as SYNC[2,4]_[A1,A2,B1,B2]_OOS, SYNC8_OOS. OVFL is referred to as SYNC[2,4]_[A1,A2,B1,B2]_OVFL,
SYNC8_OVFL.
Receive Clocking for Multi-channel Alignment – ORSO82G5
There are a total of nine clocks for the receive path, from FPGA to the core. The four used in SONET mode are
RSYSCLKA1 and RSYSCLKA2 (both for block A), and RSYSCLKB1 and RSYSCLKB2 (both for block B). The fol-
lowing diagrams show the recommended clock distribution approaches for SONET mode multi-channel alignment
modes. Cell mode alignment is discussed in the section describing the Input Port Controller (IPC).)
SONET Mode Twin Alignment
Figure 27 describes the clocking scheme for twin alignment in the ORSO82G5. In twin alignment, the valid channel
pairs are AA,AB and AC,AD in block A and BA,BB and BC,BD in block B. The gure provides the clocking scheme
for block A as an example. RSYSCLKA1 should be sourced from RWCKAA or RWCKAB. RSYSCLKA2 should be
sourced from RWCKAC or RWCKAD. This clocking approach provides the required 0 ppm clock frequency match-
ing for each pair and provides exibility in applications where the two pairs in the block are received from asynchro-
nous sources or operate at different rates.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSPI4 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC |
| ORSPI4-1F1156C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSPI4-1F1156I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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