參數資料
型號： ORSO82G5-3FN680C
廠商： Lattice Semiconductor Corporation
文件頁數： 111/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
60
Figure 46. ORSO82G5 Receive FPGA/Embedded Core Interface IPC8 Mode
In the SERDES-only mode the data are simply transferred as 32-bit wide words to and from the FPGA logic. The
next sections describe the signal denitions for the TX and RX paths in the SONET, OPC2 and OPC8 modes. The
signal names unique to an operating mode are preferred for design and are generally the ones used in the
ispLEVER design environment. The labels in the left most column are the hardware FPGA interface names. The
ispLEVER software creates an HDL module with specic names based on the mode selected for each channel.
The pin mappings performed by ispLEVER are shown in Table 11 through Table 14.
The interface signals for the embedded RAM are completely independent of these signals. The memory signals are
described in a later section.
Signal Description for TX Path (FPGA to SERDES Core) – ORSO42G5
Signals are divided across four channels with 40 signals per channel. TXDxx[39:0] is the set of 40 signals for a
channel xx.
The data signals multiplexing scheme is similar to the one used for the RXD signals. However, the status signals
multiplexing is different. Please refer to Table 11 for a detailed description of the TXD multiplexing scheme.
For all channels the TXDxx[39:33] signals are not used.
Table 11 summarizes the signals at the FPGA/Core interface in the transmit direction.
SYSCLK156x[1,2]
IPC8_CELLSTART
D
DDD
D
DD
D
DDDD
“n” clk cycles
4 clk cycles
CELL BIP ERROR
If a Cell BIP Error occurs, the CELL_BIP_ERR signal
reects the occurrence, as shown in the figure.
D
IPC8_CELL_BIP_ERR
IPC8_CELLDROP
IPC8_[159:0]
BIP Error is associated
with CURRENT cell
Cell Drop is associated with
the NEXT cell (NOT present)
CELL BIP ERROR
If a cell error occurs within the ASB and;
1. CELL_BIP_INH=0 (Do not drop BIP errored cells)
2. A BIP error occurs
The drop indicator will PRECEED the user cell that con-
tains the BIP error. All data will be passed w/o modica-
tion.
1 cycle
IDLE
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參數描述
ORSO82G5-3FN680C1 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-G2-PAC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSPI4 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-1F1156C 功能描述:FPGA - 現場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSPI4-1F1156I 功能描述:FPGA - 現場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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