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參數(shù)資料
| 型號： | NT5SV16M16AT-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Synchronous DRAM |
| 中文描述： | 256Mb的同步DRAM |
| 文件頁數(shù)： | 8/65頁 |
| 文件大小： | 814K |
| 代理商： | NT5SV16M16AT-75B |
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NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
8
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits
A7 - A12, BA0, and BA1.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst
sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a
Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organi-
zation: x4, x8, or x16).
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the
device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with
single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to
read cycles. All write cycles are single write operations when this mode is selected.
Note:
Page length is a function of I/O organization and column addressing.
x4 organization (CA0-CA9, CA11); Page Length = 2048 bits
x8 organization (CA0-CA9); Page Length = 1024 bits
x16 organization (CA0-CA8); Page Length = 512 bits
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
2
x x 0
0, 1
0, 1
x x 1
1, 0
1, 0
4
x 0 0
0, 1, 2, 3
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
相關PDF資料 |
PDF描述 |
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| NT5SV16M16AT-75BL | 256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 256Mb Synchronous DRAM |
| NT5SV16M16AT-8B | 256Mb Synchronous DRAM |
| NT5SV16M16AT-8BL | 256Mb Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV16M16AT-75BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-8BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
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