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| 型號： | NT5SV16M16AT-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Synchronous DRAM |
| 中文描述： | 256Mb的同步DRAM |
| 文件頁數(shù)： | 28/65頁 |
| 文件大?。?/td> | 814K |
| 代理商： | NT5SV16M16AT-75B |
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NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
28
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAM’ s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
Clock Suspend during a Read Cycle
Clock Suspend during a Write Cycle
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
CKE
DQs
DOUT A
0
DOUT A
2
DOUT A
1
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DOUT element at the DQs when the
suspend operation starts is held valid
(Burst Length = 4, CAS Latency = 2)
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
CKE
DQs
DIN A
2
DIN A
3
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DIN is masked during the Clock Suspend Period
DIN A
1
DIN A
0
(Burst Length = 4, CAS Latency = 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5SV16M16AT-75BL | 256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 256Mb Synchronous DRAM |
| NT5SV16M16AT-8B | 256Mb Synchronous DRAM |
| NT5SV16M16AT-8BL | 256Mb Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV16M16AT-75BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-8BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
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