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參數(shù)資料
| 型號(hào)： | NT5SV16M16AT-8B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Synchronous DRAM |
| 中文描述： | 256Mb的同步DRAM |
| 文件頁數(shù)： | 1/65頁 |
| 文件大小： | 814K |
| 代理商： | NT5SV16M16AT-8B |
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NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
1
REV 1.0
May, 2001
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
8192 refresh cycles/64ms
Random Column Address every CK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package:
54-pin 400 mil TSOP-Type II
-7K parts for PC133 2-2-2 operation
-75B parts for PC133 3-3-3 operation
-8B parts for PC100 2-2-2 operation
Description
The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT
are four-bank Synchronous DRAMs organized as 16Mbit x 4
I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 133MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC’ s
advanced 256Mbit single transistor CMOS DRAM process
technology.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Thirteen row addresses (A0-A12) and two
bank select addresses (BA0, BA1) are strobed with RAS.
Eleven column addresses (A0-A9, A11) plus bank select
addresses and A10 are strobed with CAS. Column address
A11 is dropped on the x8 device, and column addresses A11
and A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A12, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 133MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
-7K
3
CL=2
-75B,
CL=3
-8B,
CL=2
Units
f
CK
t
CK
t
AC
t
AC
Clock Frequency
133
133
100
MHz
Clock Cycle
Clock Access Time
1
7.5
7.5
10
ns
—
—
—
ns
Clock Access Time
2
5.4
5.4
6
ns
1. Terminated load. See AC Characteristics on page 37.
2. Unterminated load. See AC Characteristics on page 37.
3. t
RP
= t
RCD
= 2 CKs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5SV16M16AT-8BL | 256Mb Synchronous DRAM |
| NT5SV32M8AT | 256Mb Synchronous DRAM |
| NT5SV32M8AT-75B | 256Mb Synchronous DRAM |
| NT5SV32M8AT-7K | 256Mb Synchronous DRAM |
| NT5SV32M8AT-8B | 256Mb Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV16M16AT-8BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M4DT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV16M4DT-6K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV16M4DT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV16M4DT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
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