參數(shù)資料
型號: NSC800D
廠商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁數(shù): 50/76頁
文件大?。?/td> 785K
代理商: NSC800D
12.10 Exchanges
(Continued)
EXX
Exchange the contents of the BC, DE, and HL registers with
their corresponding alternate register.
BC
Y
B’C’
No flags affected
DE
Y
D’E’
HL
Y
H’L’
7
6
5
4
3
2
1
0
1
1
0
1
1
0
0
1
Timing:
M cycles D 1
T states D 4
Addressing Mode:
Implied
REGISTER/MEMORY
EX
(SP), ss
Exchange the two bytes at the top of the external memory
stack with the 16-bit register ss.
(SP)
Y
SS
L
No flags affected
(SP
a
1)
Y
SS
H
7
6
5
4
3
2
1
0
1
1
1
0
0
0
1
1
EX (SP), HL
Timing:
M cycles D 5
T states D 19 (4, 3, 4, 3, 5)
Addressing Mode:
7
6
5
Register/Register Indirect
4
3
2
1
0
EX (SP), IX (for N
X
e
0)
1
1
N
X
1
1
1
0
1
EX (SP),IY (for N
X
e
1)
1
1
1
0
0
0
1
1
Timing:
M cycles D 6
T states D 23 (4, 4, 3, 4, 3, 5)
Addressing Mode:
Register/Register Indirect
12.11 Memory Block Moves and
Searches
SINGLE OPERATIONS
LDI
Move data from memory location (HL) to memory location
(DE), increment memory pointers, and decrement byte
counter BC.
(DE)
w
(HL)
S: N/A
DE
w
DE
a
1
Z: N/A
HL
w
HL
a
1
H: Reset
BC
w
BC
b
1
P/V: Set if BC
b
1
i
0, other-
wise reset
N: Reset
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
Timing:
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
LDD
Move data from memory location (HL) to memory location
(DE), and decrement memory pointer and byte counter BC.
(DE)
w
(HL)
S: N/A
DE
w
DE
b
1
Z: N/A
HL
w
HL
b
1
H: Reset
BC
w
BC
b
1
P/V: Set if BC
b
1
i
0, other-
wise reset
N: Reset
C: N/A
0
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
0
1
0
0
0
Timing:
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
CPI
Compare data in memory location (HL) to the Accumulator,
increment the memory pointer, and decrement the byte
counter. The Z flag is set if the comparison is equal.
A
b
S: Set if result of comparison sub-
tract is negative
HL
w
HL
a
1
BC
w
BC
b
1
Z: Set if result of comparison is
Z
w
1
zero
if A
e
(HL)
H: Set according to borrow from
bit 4
P/V: Set if BC
b
1
i
0, otherwise
reset
N: Set
C: N/A
1
0
7
6
5
4
3
2
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
1
Timing:
M cycles D 4
T states D 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
CPD
Compare data in memory location (HL) to the Accumulator,
and decrement the memory pointer and byte counter. The Z
flag is set if the comparison is equal.
A
b
(HL)
S: Set if result is negative
HL
w
HL
b
1
Z: Set if result of comparison is
zero
BC
w
BC
b
1
H: Set according to borrow from
Z
w
1
bit 4
if A
e
(HL)
P/V: Set if BC
b
1
i
0, otherwise
reset
N: Set
C: N/A
50
相關PDF資料
PDF描述
NSC800E NSC800TM High-Performance Low-Power CMOS Microprocessor
NSC800N NSC800TM High-Performance Low-Power CMOS Microprocessor
NSC800V NSC800TM High-Performance Low-Power CMOS Microprocessor
NSC858 NSC858 Universal Asynchronous Receiver/Transmitter
NSC858D NSC858 Universal Asynchronous Receiver/Transmitter
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