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參數(shù)資料
| 型號： | NSC800D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁數(shù)： | 24/76頁 |
| 文件大小： | 785K |
| 代理商： | NSC800D |
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9.0 Timing and Control
(Continued)
so that the complete state of the CPU just prior to the non-
maskable interrupt may be restored. The method of restor-
ing the status of IFF
1
is through the execution of a Return
Non-Maskable Interrupt (RETN) instruction. Since this in-
struction indicates that the non-maskable interrupt service
routine is completed, the contents of IFF
2
are now copied
back into IFF
1
, so that the status of IFF
1
just prior to the
acceptance of the non-maskable interrupt will be automati-
cally restored.
Figure 19 depicts the status of the flip flops during a sample
series of interrupt instructions.
Interrupt Control Register.
The interrupt control register
(ICR) is a 4-bit, write only register that provides the program-
mer with a second level of maskable control over the four
maskable interrupt inputs.
The ICR is internal to the NSC800 CPU, but is addressed
through the I/O space at I/O address port X’BB. Each bit in
the register controls a mask bit dedicated to each maskable
interrupt, RSTA, RSTB, RSTC and INTR. For an interrupt
request to be accepted on any of these inputs, the corre-
sponding mask bit in the ICR must be set (
e
1) and IFF
1
and IFF
2
must be set. This provides the programmer with
control over individual interrupt inputs rather than just a sys-
tem wide enable or disable.
TL/C/5171–26
Bit
0
1
2
3
Name
IEI
IEC
IEB
IEA
Function
Interrupt Enable for INTR
Interrupt Enable for RSTC
Interrupt Enable for RSTB
Interrupt Enable for RSTA
For example: In order to enable RSTB, CPU interrupts must
be enabled and IEB must be set.
At reset, IEI bit is set and other mask bits IEA, IEB, IEC are
cleared. This maintains the software compatibility between
NSC800 and Z80A.
Execution of an I/O block move instruction will not affect
the state of the interrupt control bits. The only two instruc-
tions that will modify this write only register are OUT (C), r
and OUT (N), A.
Operation
Initialize
#
#
#
EI
#
#
#
INTR
IFF
1
0
IFF
2
0
Comment
Interrupt Disabled
1
1
Interrupt Enabled after
next instruction
0
0
Interrupt Disable and INTR
Being Serviced
#
#
#
EI
1
1
Interrupt Enabled after
next instruction
Interrupt Enabled
RET
#
#
#
NMI
#
#
#
RETN
#
INTR
#
#
#
NMI
#
#
#
RETN
#
#
#
EI
1
1
0
1
Interrupt Disabled
1
1
Interrupt Enabled
0
0
Interrupt Disabled
0
0
Interrupt Disabled and NMI
Being Serviced
0
0
Interrupt Disabled and INTR
Being Serviced
1
1
Interrupt Enabled after
next instruction
Interrupt Enabled
RET
#
#
#
1
1
FIGURE 19. IFF
1
and IFF
2
States Immediately after the
Operation has been Completed
24
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| NSC800E | NSC800TM High-Performance Low-Power CMOS Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
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| NSC800D/883C | 制造商: 功能描述: 制造商:undefined 功能描述: |
| NSC800D/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| NSC800D-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
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