參數(shù)資料
型號(hào): NSC800D
廠商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁數(shù): 5/76頁
文件大?。?/td> 785K
代理商: NSC800D
4.0 AC Electrical Characteristics
V
CC
e
5V
g
10%, GND
e
0V, unless otherwise specified (Continued)
Symbol
Parameter
NSC800-1
NSC800-3
NSC800-35
NSC800-4
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
T
H(ADH)1
A(8–15) Hold Time During
Opcode Fetch
0
0
0
0
ns
T
H(ADH)2
A(8–15) Hold Time During
Memory or IO, RD and WR
400
100
85
60
ns
T
H(ADL)
AD(0–7) Hold Time
100
60
35
30
ns
T
H(WD)
Write Data Hold Time
400
100
85
75
ns
t
INH
Interrupt Hold Time
0
0
0
0
ns
t
INS
Interrupt Set-Up Time
100
50
50
45
ns
t
NMI
Width of NMI Input
50
30
25
20
ns
t
RDH
Data Hold after Read
0
0
0
0
ns
t
RFLF
RFSH Rising to ALE
Falling
60
50
45
40
ns
t
RL(MR)
RD Rising to ALE Rising
(Memory Read)
390
100
50
45
ns
t
S(AD)
AD(0–7) Set-Up Time
300
45
45
40
ns
t
S(ALE)
A(8–15), SO, SI, IO/M
Set-Up Time
350
70
55
50
ns
t
S(WD)
Write Data Set-Up Time
385
75
35
30
ns
t
W(ALE)
ALE Width
430
130
115
100
ns
t
WH
WAIT Hold Time
0
0
0
0
ns
t
W(I)
Width of INTR, RSTA-C,
PS, BREQ
500
200
140
125
ns
t
W(INTA)
INTA Strobe Width
1000
400
225
200
ns
Add two t states for first
INTA of each interrupt
response string Add t for
each WAIT state
t
WL
WR Rising to ALE Rising
450
130
70
70
ns
t
W(RD)
Read Strobe Width During
Opcode Fetch
960
360
210
185
ns
Add t for each WAIT
State Add t/2 for Memory
Read Cycles
t
W(RFSH)
Refresh Strobe Width
1925
725
450
395
ns
t
WS
WAIT Set-Up Time
100
70
60
55
ns
t
W(WAIT)
WAIT Input Width
550
250
195
175
ns
t
W(WR)
Write Strobe Width
985
370
250
220
ns
Add t for each WAIT state
t
XCF
XIN to Clock Falling
25
100
15
95
5
90
5
80
ns
t
XCR
Note 1:
Test conditions: t
e
1000 ns for NSC800-1, 400 ns for NSC800, 285 ns for NSC800-35, 250 ns for NSC800-4.
XIN to Clock Rising
25
85
15
85
5
90
5
80
ns
Note 2:
Output timings are measured with a purely capacitive load of 100 pF.
5
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