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參數(shù)資料
| 型號(hào)： | NSBMC096VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSBMC096-16/-25/-33 Burst Memory Controller |
| 中文描述： | NSBMC096-16/-25/-33突發(fā)內(nèi)存控制器 |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大小： | 266K |
| 代理商： | NSBMC096VF |
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Functional Description
(Continued)
BUFFER CONTROL MODE FIELD
The transfer of Data from the memory sub-system to the
i960
bus
occurs
through
NSBMC096. Two of the signals (LEA, LEB) provide trans-
parent latch controls for use during write cycles. LEA and
LEB have variable timing but fixed interpretation. The other
two signals, TXA and TXB, change in both timing and func-
tion according to programmed mode. Table II presents
these signals using names that are based on the function
performed.
buffers
controlled
by
the
Signals containing TX are transmit controls for buffers that
have output enables (transmit from the memory system).
Buffers such as ’245s or ’646s, which have direction and
enable pins, are controlled by CE (chip enable) in modes 1
and 3. Signals ending with A or B are specific to one or the
other of the two leaves of memory controlled by the
NSBMC096. Signals without suffixes apply to both leaves.
The signal LeafB/
*
A, required in some configurations, indi-
cates which memory leaf will be selected on the next clock
cycle.
TABLE II. Interpretation of the Buffer Control
Signals for Various Control Modes
Mode
Signal 1
Signal 2
0
1
2
3
TXA
CEA
TX
CE
TXB
CEB
LeafB/
*
A
LeafB/
*
A
Table III presents some of the possible configurations with
the corresponding mode settings. For a comprehensive dis-
cussion of the selection of a buffer strategy, refer to the
NSBMC096 Application Guide.
TABLE III. Possible NSBMC096
Memory/Buffer Configurations
Buffer
Type
DRAM
Type
Write
Access
Read
Access
Buffer
Mode
74FCT245
74FCT245
74FCT646
74FCT543
Am29C983
None
Nibble
Bit
Nibble
Bit
Bit
Nibble
2-4-4-4
*
2-4-4-4
*
1-0-0-0
1-0-0-0
1-0-0-0
2-4-4-4
*
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
Mode 3
Mode 1
Mode 3
Mode 0
Mode 2
Mode 2, 3
*
These configurations have burst writes disabled.
DRAM SIZE FIELD
This three bit field, bits 12–14, selects the DRAM device
address size, and consequently, memory block size. Note
that the memory in both leaves of a bank are required to be
of the same size and organization for correct operation. Ta-
ble IV lists the size codes and the corresponding device
sizes.
TABLE IV. Size Code Settings, DRAM
Density and Address Range Size
Memory
Size Code
Memory
Block Size
Max
Banks
Memory
Types
0 0 0
0 0 1
0 1 0
0 1 1
2 MB
8 MB
32 MB
128 MB
1
1
1
1
256k x 1
1 MB x 1
4 MB x 1
16 MB x 1
1 0 0
1 0 1
1 1 0
1 1 1
2 MB
8 MB
32 MB
128 MB
4
*
4
*
4
*
4
*
64k x 4
256k x 4
1 MB x 4
4 MB x 4
*
Note that banks are sequentially addressed within a block.
REFRESH RATE FIELD
The system clock frequency is used to derive the period of
DRAM refresh cycles. The refresh rate is calculated as
(PCLK clock frequency) / (16 x (programmed value
a
1)).
If, for example, the system clock is 25 MHz and the pro-
grammed value is 24 (0x18), the NSBMC096 will execute
the 256 refresh cycles for a 256k DRAM in 4.096 ms.
The algorithm employed by the NSBMC096 guarantees the
time for complete device refresh, however, individual row
refresh may be delayed so as not to pre-empt bursts in
progress. Since the maximum burst is 6 clock cycles in
length, this delay in no way endangers data integrity. Ac-
cess to devices other than NSBMC096 controlled memory
are not delayed by refresh, access to memory while refresh
is in progress are completed once the refresh cycle is com-
plete.
TIMER CONTROL FIELD
The 24-bit timer is a counter which scales PCLK by a pro-
grammable amount and automatically reloads when termi-
nal count is reached. The contents of the timer cannot be
read directly, however, the counter will generate an interrupt
when terminal count is reached. The timer is disabled fol-
lowing a RESET and the
Timer Reload
value (Configuration
Bytes 4–6) must be programmed before the timer is en-
abled.
The terminal count interrupt can be generated to comply
with either edge triggered or level sense interrupt control-
lers. Edge triggered mode generates a pulse that is low for
two cycles when terminal count is reached. In Level sense
mode, the output is asserted low when terminal count is
reached and the output remains low until the Acknowledge
Timer Interrupt op-code is written to configuration byte 0.
See the section on Operation Control for further detail con-
cerning timer interrupt control.
BUS WATCH TIMER CONTROL FIELD
The NSBMC096 contains circuitry that monitors all bus ac-
cess requests regardless of the target address. Access
made to a region configured for external ready can hang the
processor if for some reason READY is not returned to ter-
minate the access. The NSBMC096 can detect such a con-
dition and if the bus watch feature is enabled, will return
READY and BERR.
8
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| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類(lèi)型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
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