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參數(shù)資料
| 型號： | NSBMC290-16 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 318K |
| 代理商： | NSBMC290-16 |
TL/V/11803
N
July 1993
NSBMC290
TM
-16/-20/-25/-33
Burst Mode Memory Controller
General Description
The
NSBMC290
V29BMC
TM
. The NSBMC290 Burst Mode Memory Control-
ler is a single chip device designed to simplify the imple-
mentation of burst mode access in high performance sys-
tems using the Am29000
TM
Streamlined Instruction Proces-
sor.
is
functionally
equivalent
to
the
The extremely high instruction rate achieved by this proces-
sor places extraordinary demands on memory system de-
signs if maximum throughput is to be sustained and costs
minimized.
The most obvious solution to the problem of access speed
is to implement system memory using high-speed static
memories. However, the high cost and low density of these
devices make them an expensive and space consumptive
solution.
A more cost effective method of solving this problem is via
the use of dynamic RAMs. Their high density and low cost
make their use extremely attractive. The impediment to their
use is their relatively slow access times.
However when operated in page mode, dynamic RAMs be-
have more like static memories. Properly managed, they
can yield access times approaching those of fully static
RAMs.
The function of NSBMC290 is to interface the page mode
access protocol of dynamic RAMs with the more general
burst mode access protocol supported by the Am29000 lo-
cal channel. The device manages a double banked arrang-
ment of dynamic RAMs such that when burst accesses are
permitted data can be read, or written, at the rate of one
word per system clock cycle.
Packaged as a 124 pin PGA or 132 pin PQFP, the
NSBMC290 drives memory arrays directly, thus minimizing
design complexity and package count.
Features
Y
Interfaces directly to Am29000 Local Channel
Y
Manages Page Mode Dynamic Memory devices
Y
Supports DRAMs from 64 KB to 16 MB
Y
Manages Instruction and/or Data Memory
Y
Very Low Power Consumption
Y
On-Chip Memory Address Multiplexer/Drivers
Y
Flexible Instruction/Data Bus Buffer Management
Y
Software-Configured operational parameters
Y
Auto-Configured Bank Size and Location
Y
High-Speed CMOS Technology
Block Diagram
Typical System Configuration
TL/V/11803–1
Logic Symbol
TL/V/11803–2
This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information
is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications
of this product without notice.
TRI-STATE
é
is a registered trademark National Semiconductor Corporation.
NSBMC290
TM
is a trademark of National Semiconductor Corporation.
V29BMC
TM
is a trademark of V3 Corporation.
Am29000
TM
is a trademark of Advanced Micro Devices, Sunnyvale, California, USA.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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| NSBMC290UP | Burst Mode Memory Controller |
| NSBMC290VF | Burst Mode Memory Controller |
| NSC800 | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800D | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800E | NSC800TM High-Performance Low-Power CMOS Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC290UP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Burst Mode Memory Controller |
| NSBMC290UP-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290UP-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290UP-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290UP-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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