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參數(shù)資料
| 型號(hào)： | NSBMC290-16 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Mode Memory Controller |
| 中文描述： | 突發(fā)模式內(nèi)存控制器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 318K |
| 代理商： | NSBMC290-16 |
Functional Description
(Continued)
INTERCONNECT DETAILS
The NSBMC290 may be applied in designs where instruc-
tion and data memories are separated
or
in designs where
a single memory space is used for both instruction and data.
In split instruction/data designs, the control signals for the
address space
not
required are simply pulled up to V
CC
levels and not connected to the corresponding local chan-
nel signals.
TABLE V. Control Signal Set Unique
to Instruction Accesses
Signal Type
Signal Names
Input
IREQ, IBREQ, IREQT, PIA
Output
IBACK, IRDY
Buffer Control
IBTXA, IBTXB, IBTX, BANKB/
*
A
TABLE VI. Control Signal Set Unique to Data Accesses
Signal Type
Signal Names
Input
DREQ, DBREQ, DREQT
[
1..0
]
,
OPT
[
2..0
]
PDA
Output
DBACK, DRDY
Buffer Control
DBCEA,B, DBCE, DBTXA,B,
DBTX, BANKB/
*
A
For mixed instruction and data designs, all local channel
signals must be connected. Tables V and VI detail the con-
trol signal sets required for the NSBMC290 to control the
corresponding address spaces. It is recommended that all
control signals be connected and that instruction and data
space segregation be done via software allocation and/or
use of the Am29000 internal Translation Look-Aside Buffer.
Typical Application
SYSTEM IMPLEMENTATION AND DESIGN
The ease with which the NSBMC290 may be integrated into
a system design is illustrated in the diagram inFigure 2. The
system shown supports an Am29000 with between 2 MB
and 32 MB of memory (depending on the storage devices
selected) managed by a single NSBMC290. This specific
example accommodates 256k x 1, 1 MB x 1 or 4 MB x 1
devices.
In a minimal system configuration only one NSBMC290 is
required. This is because the NSBMC290 manages both in-
struction and data access to a memory block. However, with
a single memory block, instruction and data accesses can-
not be overlapped and the number of burst access restarts
is a function of the way in which the software is designed. It
is therefore difficult to predict performance degradation.
If maximum performance is required, the addition of one or
more NSBMC290s is an effective solution. Our bench marks
indicate that for systems with physically separated instruc-
tion and data space performance is degraded by approxi-
mately 5% over the theoretical rate achieved in system de-
signs employing high speed static RAMs. The device count
and cost of these solutions, however, differ by at least a
factor of 6.
With the exception of data buffers external components are
not required, except to terminate the address and control
lines to the memory array. The use of passive components
arranged in a serial or parallel terminating network is a sim-
ple but effective method of implementing this requirement.
9
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| NSBMC290UP | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Burst Mode Memory Controller |
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| NSBMC290UP-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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