參數(shù)資料
型號(hào)： NSBMC290-16
廠商： National Semiconductor Corporation
英文描述： Burst Mode Memory Controller
中文描述： 突發(fā)模式內(nèi)存控制器
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 318K
代理商： NSBMC290-16
Pin Descriptions
(Continued)
MEMORY INTERFACE
The NSBMC290 is designed to drive a memory array orga-
nized as 2 banks each of 32 bits. The address and control
signals for the memory array are output through high current
drivers in order to minimize the propagation delay due to
memory input impedance and trace capacitance. External
array drivers are not required. The address and control sig-
nals, however, must be externally terminated.
Pin
Description
A(A,B)0–10
Multiplexed Addresses (Output; High Current):
These two buses transfer the multiplexed row and column
addresses to the memory array banks A and B respectively.
RAS(A,B)
Row Address Strobes (Output; High Current, Active Low):
These signals are strobes that indicate the
existence of a valid row address on A(A,B)0–10. These signals are to be connected to the two interleaved banks
of memory. One is assigned to each bank.
CAS(A,B)0-3
Column Address Strobe (Output; High Current, Active Low):
These signals are strobes that indicate a valid
column address on A(A,B)0–10. A set of each of these (A,B) are assigned to each memory bank, and within each
set, one is assigned to each byte of the 32-bit memory.
MWE(A,B)
Memory Write Enable (Output; High Current, Active Low):
These signals are the write strobes for the DRAM
memories. One is supplied for each of the two banks of memory although they are logically identical.
BUFFER CONTROLS
In order not to limit system implementation strategies vis
j
vis instruction and data bus organization, the NSBMC290
permits the designer to keep these busses separate or not
as performance criteria dictate. In order to maintain bus
separation, data buffers are required. In order to maximize
performance, these buffers are controlled directly by the
NSBMC290.
Pin
Description
DBLE(A,B)
Data Bus Latch Enable A and B (Output; Active High):
These outputs are used to enable transparent latches to
latch data from the Processor data bus to each bank of memory during a write cycle (Data access only).
The following buffer control outputs are multi-mode signals. The signal names, as they appear on the logic symbol,
are the default signal names (Mode
e
0). A more complete description is presented in the configuration section.
DBTX(A,B)
Data Bus Transmit A and B (Output; Active Low):
These outputs are used during read cycles to enable data
from the individual banks of memory to drive the data bus.
IBTX(A,B)
Instruction Bus Transmit A and B (Output; Active Low):
These outputs are used during instruction cycles to
enable data from the individual banks of memory to drive the instruction bus.
5
相關(guān)PDF資料
PDF描述
NSBMC290UP Burst Mode Memory Controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NSBMC290UP 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Burst Mode Memory Controller
NSBMC290UP-16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NSBMC290UP-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NSBMC290UP-25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NSBMC290UP-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
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