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參數(shù)資料
| 型號： | NSBMC096VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSBMC096-16/-25/-33 Burst Memory Controller |
| 中文描述： | NSBMC096-16/-25/-33突發(fā)內(nèi)存控制器 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 266K |
| 代理商： | NSBMC096VF |
Application Example
System Clock:
25 MHz
16
m
s per row
(0
c
18)
1 MB x 1
(Size
e
1)
Signal 1
e
CEA, Signal 2
e
CEB
(Mode 1)
Refresh Rate:
Memory Size:
Buffer Mode:
Interleave:
Enabled
Row Address Hold:
(/2
clock cycle
(
Row Address Hold
e
0)
Cycle Extend:
Disabled
(3 clock RAS derived from
t
RSHL
of NSBMC096, RAS access time
of DRAM, buffer delay of 74FCT245
and setup time of the processor’s data
inputs)
Burst Write:
Disabled
Base Address:
8 MB
(0b000000000100)
Required Configuration for startup
0000
0000
1000
1000
1001
0110
0000
0000
(0x00889600)
Configuration Setup
0xFF0F0000 (0xFF0F0000, 0);
0xFF0F0658 (0xFF0F0400
a
(0x96
m
2), 0);
0xFF0F0A20 (0xFF0F0800
a
(0x88
m
2), 0);
0xFF0F0C00 (0xFF0F0C00, 0);
/
*
Config. bits 7..0
e
0
*
/
/
*
Config. bits 15..8
e
0
*
/
/
*
Config. bits 23..16
e
0
*
/
/
*
Config. bits 31..24
e
0
*
/
The ease with which the NSBMC096 may be integrated into
a system design is illustrated in the diagram inFigure 4. The
system shown supports an i960 CA/CF with between 2 and
128 MB of memory, depending on the devices selected,
managed by a single NSBMC096. This specific example ac-
commodates 1 MB x 1, 4 MB x 1 or 16 MB x 1 devices.
Connection of the NSBMC096 to the i960 CA/CF processor
is accomplished simply by wiring together pins with the
same names. The only exceptions are READY and BTERM.
If the NSBMC096 is the only device that generates these
two signals, they can be connected directly to the appropri-
ate inputs of the processor and require only a small pull up
resistor to keep them de-asserted when in the high imped-
ance state.
If multiple processor peripherals are connected to READY
or BTERM, 3-state drivers should be used in such a manner
that the signals are actively de-asserted prior to the driver
being placed in its’ high impedance state. If this rule is fol-
lowed, a simple ‘‘wire or’’ can be used. Alternately, all
sources of READY or BTERM can be combined using multi-
ple input gates and the processor signals driven by the out-
puts.
TL/V/11805–7
FIGURE 4. Possible System Interconnection using V96BMC
(Mode 1 where TXA is used as CEA and TXB as CEB)
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| NSBMC096VF-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC290 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NSBMC290-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Burst Mode Memory Controller |
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