參數(shù)資料
型號(hào): NSBMC096-16
廠商: National Semiconductor Corporation
英文描述: NSBMC096-16/-25/-33 Burst Memory Controller
中文描述: NSBMC096-16/-25/-33突發(fā)內(nèi)存控制器
文件頁數(shù): 1/18頁
文件大小: 266K
代理商: NSBMC096-16
TL/V/11805
N
August 1993
NSBMC096-16/-25/-33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
circuit which implements all aspects of DRAM control for
high
performance
systems
SuperScalar Embedded Processor. The NSBMC096 is func-
tionally equivalent to the V96BMC
TM
.
using
an
i960
é
CA/CF
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized.
Static RAM offers a simple solution for high speed memory
systems. However, high cost and low density make this an
expensive and space consumptive choice.
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost. Their drawbacks are, slower access time
and more complex control circuitry required to operate
them.
The access time problem is solved if DRAMs are used in
page mode. In this mode, access times rival that of static
RAM. The control circuit problem is resolved by the
NSBMC096.
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA/CF to the
page mode access protocol supported by dynamic RAMs.
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access, data can be
read, or written, at the rate of one word per system clock
cycle.
The NSBMC096 has been designed to allow maximum flexi-
bility in its application. The full range of processor speeds is
supported for a wide range of DRAM speeds, sizes and or-
ganizations.
No glue logic is required because the bus interface is cus-
tomized to the i960 CA/CF. System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip.
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1.3 square inches. It reduces design complexi-
ty, space requirements and is fully derated for loading, tem-
perature and voltage.
Features
Y
Interfaces directly to the i960 CA
Y
Integrated Page Cache Management
Y
Manages Page Mode Dynamic Memory devices
Y
On-chip Memory Address Multiplexer/Drivers
Y
Supports DRAMs trom 256 kB to 64 MB
Y
Bit counter/timer
Y
Non-interleaved or two way interleaved operation
Y
5-Bit Bus Watch Timer
Y
Software-configured operational parameters
Y
High-Speed/Low Power CMOS technology
Block Diagram
TL/V/11805–1
This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information
is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications
of this product without notice.
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
NSBMC096
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation.
i960
is a registered trademark of Intel Corporation.
V96BMC
TM
is a trademark of V3 Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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