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參數資料
| 型號： | NSBMC033 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲控制器) |
| 中文描述： | 突發(fā)內存控制器（脈沖存儲控制器） |
| 文件頁數： | 5/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | NSBMC033 |
Pin Descriptions
(Continued)
MEMORY INTERFACE
The NSBMC960 is designed to drive a memory array orga-
nized as 2 leaves each of 32 bits. The address and control
signals for the memory array are output through high current
drivers in order to minimize propagation delay due to input
impedance and trace capacitance. External array drivers
are not required. The address and control signals, however,
should be externally terminated.
Pin
Description
A(A,B)0–11
Multiplexed Address Bus (Output; 24 mA):
These two buses transfer the multiplexed row and column
addresses to the memory array leaves A and B. When non-interleaved operation is selected, only address bus A
should be used.
RAS(A,B)0–3
Row Address Strobes (Output; 12 mA Active Low):
These strobes indicate the presence of a valid row
address on busses A(A,B)0–11. These signals are to be connected one to each leaf of memory. Four banks of
interleaved memory may be attached to a NSBMC960.
CAS(A,B)0–3
Column Address Strobe (Output; 12 mA, Active Low):
These strobes latch a column address from A(A,B)0–
11. They are assigned one to each byte in a leaf.
MWE(A,B)
Memory Write Enable (Output; 24 mA, Active Low):
These are the DRAM write strobes. One is supplied for
each leaf to minimize signal loading.
REFRESH
Refresh in progress (Output; 12 mA, Active Low):
This output gives notice that a refresh cycle is to be
executed. The timing leads refresh RAS by one cycle.
BUFFER CONTROLS
Buffer control signals are provided to simplify the control of
the interface between the DRAM and i960 data busses.
Multiple operating modes facilitate choice of buffer type,
and simple bus buffers (‘‘245’’s), bus latches (‘‘543’’s) and
bus registers (‘‘646’’s) are all supported.
Pin
Description
TX(A,B)
Data Bus Transmit A and B (Output; Active Low):
These outputs are multi-function signals. The signal names,
as they appear on the logic symbol, are the default signal names (Mode
e
0). The purpose of these outputs is to
control buffer output enables during data read transactions and, in effect, control the multiplexing of data from
each memory leaf onto the i960 CA/CF data bus.
LE(A,B)
Data Bus Latch Enable A and B (Output; Active Low):
These outputs are mode independent, however, the
timing of the signals change for different operational modes. They control transparent latches that hold data
transmiffed during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each
leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to
(/2
clock.
5
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