- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363666 > NSBMC033 (National Semiconductor Corporation) Burst Memory Controller(脈沖存儲(chǔ)控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | NSBMC033 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲(chǔ)控制器) |
| 中文描述： | 突發(fā)內(nèi)存控制器（脈沖存儲(chǔ)控制器） |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 266K |
| 代理商： | NSBMC033 |
Pin Descriptions
(Continued)
i960 CA/CF INTERFACE
The following pins are functionally equivalent to those on
the i960 CA/CF from which their names are taken. Like
named pins on the i960 CA/CF and the NSBMC960 are to
be wired together. All 3-State outputs are to be weakly
pulled up to V
CC
. In typical situations, a 10 k
X
resistor is
sufficient.
Pin
Description
A2–31
Address Bus (Input):
This system bus is a word address which determines the location at which an access is
required.
ADS
Address Strobe (Input; Active Low):
Indicates that a new access cycle is being started.
D/
*
C
Data/
*
Code (Input):
Signals whether an access is for data or instructions.
BLAST
Burst Last (Input; Active Low):
Indicates that the last cycle of a burst is in progress.
DEN
Data Enable (Input; Active Low):
This input is monitored by the Bus Watch Timer to detect a bus access not
returning READY.
BTERM
Burst Terminate (Output; 3-State; Active Low):
This output is used to request termination of a burst in progress.
Used to disable burst writes.
READY
Data Ready (Output; 3-State; Active Low):
The READY output is used to signal that data on the processor bus is
valid for Read, or that data has been accepted for Write.
RESET
Reset (Input; Active Low):
Assertion of this input sets the NSBMC960 to its initial state. Following initialization, the
NSBMC960 must be configured before any memory access is possible.
BE0–3
Byte Enable (Input; Active Low):
These inputs are used to determine which byte(s) within the addressed word are to
be accessed.
W/
*
R
WRITE/
*
READ (Input):
This input indicates the direction which data is to be transferred to/from on the data bus.
SUP
Supervisor (Input; Active Low):
Indicates that the processor is operating in supervisor mode. Required for access to
configuration registers.
PCLK
System Clock (Input):
Processor output clock required to operate and synchronize NSBMC960 internal functions.
BERR
Bus Error (Output; Active Low):
When enabled, this signal is generated by the Bus Watch Circuit to prevent
processor lock-up on access to a region that is not responding.
INT
Interrupt (Output; 12 mA; Active Low):
This signal is assented when the 24-bit counter reaches terminal count and
interrupt out is enabled. May be programmed for pulse or handshake operation.
ID0–2
Chip ID (Input):
These inputs select the address offset of the NSBMC960 configuration registers. Each NSBMC960 in
a system must have a unique address for proper operation.
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSBMC096VF | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096-16 | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC290-16 | Burst Mode Memory Controller |
| NSBMC290UP | Burst Mode Memory Controller |
| NSBMC290VF | Burst Mode Memory Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NSBMC096-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。