參數(shù)資料
型號: NJU6677CL
廠商: New Japan Radio Co., Ltd.
英文描述: 88-common x 132-segment BIT MAP LCD DRIVER
中文描述: 88共同× 132段位圖,多媒體播放器
文件頁數(shù): 9/45頁
文件大?。?/td> 470K
代理商: NJU6677CL
NJU6677
(1) Description for each blocks
(1-2)Display Start Line Register
The Display start Line Register is a pointer register which indicates the address in the Display Data RAM
corresponding with COM
0
(normally it display the top line in the LCD Panel). This register also operates for
vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the
display start address of the Display Data RAM represented in 8-bit to this register.
Functional Description
(1-1) Busy Flag (BF)
While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status
read are inhibited .
The busy flag goes to “1” from D
7
terminal when status read instruction is executed.
When enough cycle time over than t
CYC
indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no
need to check the busy flag for reduction of the MPU loads.
(1-3) Line Counter
The Line Counter generates the line address of display data RAM by the count up operation synchronizing the
common cycle after the reset operation at the status change of internal FR signal.
(1-4) Column Address Counter
The column address counter is 8-bit pre-settable counter addressing the column address of display data RAM
as shown in Fig. 1. It is incremented (+1) up to (84)
H
by the Display Data Read/Write instruction execution.
It stops the count up operation at (84)
H
, and it does not count up non existing address area over than (84)
H
the count lock function. This count lock is released by new column address set.
The column address counter is independent of the Page Register.
By the Address Inverse Instruction, the column address decoder inverse the column address of Display Data
RAM corresponding to the Segment Driver.
by
(1-5) Page Register
The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses
the data with the page change, the page address set instruction is required.
(1-6) Display Data RAM
Display Data RAM is the bit map RAM consisting of 15,840 bits to memorize the display data corresponding to
each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD
panel and controls the display by following bit data.
When Normal Display : On="1" , Off="0"
When Inverse Display : On="0" , Off="1"
The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data
are set into the Display Data Latch.
The access operation from MPU to the display data RAM and the data output from the display data RAM are
so controlled to operate independently that the data rewriting does not influence with any malfunctions to the
display.The relation between column address and segment output can inverse by the Address Inverse Instruc-
tion ADC as shown in Fig.1.
(1-7) Common Driver Assignment
The scanning order can be assigned by mask option as shown on Table 1.
Table 1
COM Outputs Terminals
88
PAD No. 45
Pin name
C
0
Ver.A
Ver.B
221
264
C
43
C
87
COM
87
COM
0
C
44
COM
0
COM
87
COM
43
COM
44
COM
44
COM
43
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