參數(shù)資料
型號: NJU6677CL
廠商: New Japan Radio Co., Ltd.
英文描述: 88-common x 132-segment BIT MAP LCD DRIVER
中文描述: 88共同× 132段位圖,多媒體播放器
文件頁數(shù): 36/45頁
文件大小: 470K
代理商: NJU6677CL
NJU667
7
(5-5) Access to the Display Data RAM and Internal Register.
The NJU6677 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus
to adjust the operation frequency between MPU and the Display Data RAM or Internal Register.
For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read
cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the
next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-
holder, then it is written into the Display Data RAM by the next data write cycle.
Therefore high speed data transmission between MPU and NJU6677 is available because of it is not limited by
the t
If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the
waiting operation.
The read out operation does not read out the data in the pointed address just after the address set operation.
And second read out operation can read out the data correctly from the pointed address.
Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6.
ACC
and t
DS
as display data RAM access time and is limited by the system cycle time (R) or (W).
WR
DATA
I/O Buffer
WR
MPU
Internal
Timing
N
N+1
N+2
N+3
N
N+1
N+2
N+3
WR
DATA
I/O Buffer
WR
MPU
Internal
Timing
RD
N
N
n
n+1
Address Set N
Dummy Read
Data Read n
Data Read n+1
RD
Column Address
N
N+1
N+2
N
n
n+1
n+2
Write Operation
Read Operation
Fig.6
(5-6) Chip Select
CS is Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS=”H”, the D
0
to D
7
are high impedance and A0, RD, WR, D
7
(SI) and D
6
selected when CS=”H”,the shift register and the counter are reset. However, the reset is always operated in
any conditions of CS.
(SCL) inputs are ignored. If the serial interface is
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