參數(shù)資料
型號(hào)： NJU6677CL
廠商： New Japan Radio Co., Ltd.
英文描述： 88-common x 132-segment BIT MAP LCD DRIVER
中文描述： 88共同× 132段位圖，多媒體播放器
文件頁(yè)數(shù)： 35/45頁(yè)
文件大?。?/td> 470K
代理商： NJU6677CL
NJU667
7
(5-1) Interface type selection
NJU6677 interfaces with MPU by 8-bit bidirectional data bus (D
7
serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in
Table 5. In case of the serial interface, status and RAM data read out operation is impossible.
Table 5
P/S
Type
CS
A0
RD
H
Parallel
CS
A0
RD
L
Serial
CS
A0
-
to D
0
) or serial (SI:D
7
). The 8 bit parallel or
(5) MPU Interface
The NJU6677 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected.
68 type MPU or 80 is determined by the condition of SEL68 terminal connecting to "H" or "L" as shown in
table 6.
Table 6
(5-2) Parallel Interface
(5-3) Discrimination of Data Bus Signal
The NJU6677 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and
(RD,WR) signals as shown in Table 7.
CS
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
3
6
4
10
2
1
7
5
8
9
SI
SCL
A0
WR
WR
-
SEL68
SEL68
-
D
7
D
7
SI
D
6
D
6
SCL
D
0
to D
5
D
0
to D
5
Hi-Z
SEL68
H
L
Type
CS
CS
CS
A0
A0
A0
RD
E
RD
WR
R/W
WR
D
0
to D
7
D
0
to D
7
D
0
to D
7
68 type MPU
80 type MPU
Table 7
Common
A0
1
1
0
0
68 type
R/W
1
0
1
0
80 type
Function
RD
0
1
0
1
WR
1
0
1
0
Read Display Data
Write Display Data
Status Read
Write into the Register(Instruction)
(5-4) Serial Interface.(P/S="L")
Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when
the chip select terminal CS set to "L"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are
reset to the initial condition when the chip is not selected. The data input from SI terminal is MSB first like as
the order of D
7
,D
6
,- - - - D
0,
and the data are entered into the shift register synchronizing with the rise edge of
the serial clock SCL. The data in the shift register are converted to parallel data at the 8th serial clock rise
edge input. Discrimination of the display data or instruction of the serial input data is executed by the condi-
tion of A0 at the 8th serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RES
terminal becomes "L" or CS terminal becomes "H" before 8th serial clock rise edge, NJU6677 recognizes
them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time
chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the
SCL input.
Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface
.
Fig. 5
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