參數(shù)資料
型號: NJU6677CL
廠商: New Japan Radio Co., Ltd.
英文描述: 88-common x 132-segment BIT MAP LCD DRIVER
中文描述: 88共同× 132段位圖,多媒體播放器
文件頁數(shù): 8/45頁
文件大?。?/td> 470K
代理商: NJU6677CL
NJU6677
No
Symbol
I/O
F u n c t i o n
14
RD(E)
I
<In case of 80 Type MPU>
RD signal of 80 type MPU input terminal. Active "L"
During this signal is "L" , D
0
to D
7
terminals are output.
<In case of 68 Type MPU>
Enable signal of 68 type MPU input terminal. Active "H"
13
WR(RW)
I
<In case of 80 Type MPU>
Connect to the 80 type MPU WR signal. Actie "L".
The data on the data bus input syncronizing the rise edge of this signal.
<In case of 68 Type MPU>
The read/write control signal of 68 type MPU input terminal.
R/W
H
L
4
SEL68
I
MPU interface type selection terminal.
SEL68
3
P/S
I
serial or parallel interface selection terminal.
P/S
Chip Select
RAM data and status read operation do not work in mode of
the serial interface.
In case of the serial interface (P/S="L"),RD and WR must be fixed
"H" or "L", and D
0
to D
5
are high impedance.
9,
10
OSC
1
OSC
2
I
System clock input terminal for Maker testing.(This terminal should be Open)
For external clock operation, the clock shoud be input to OSC1 terminal.
45 to 88
C
0 to
C
43
O
LCD driving signal output terminals.
Segmet output terminals:S
0
to S
131
Common output terminals:C
0
to C
87
Segment output terminal
The following output voltages are selected by the combination of FR and data
in the RAM.(non of the n-line inverse functions)
Common output terminal
The following output voltages are selected by the combination of FR and status
of common.
89 to 220
S
0 to
S
131
O
264 to
221
C
44 to
C
87
O
H
L
State
68 Type
80 Type
Data/Command
Data
Read/Write
serial Clock
"H"
CS
A
D
0 to
D
7
RD,WR
-
"L"
CS
A0
SI(D
7
)
Write Only
SCL(D
6
)
Scan data
FR
H
L
H
L
Output Voltage
V
5
V
DD
V
1
V
4
H
L
RAM
Data
FR
Output Voltage
Normal
V
DD
V
5
V
2
V
3
Reverse
V
2
V
3
V
DD
V
5
H
H
L
H
L
L
State
Read
Write
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