參數(shù)資料
型號： NJU6677CL
廠商： New Japan Radio Co., Ltd.
英文描述： 88-common x 132-segment BIT MAP LCD DRIVER
中文描述： 88共同× 132段位圖，多媒體播放器
文件頁數(shù)： 15/45頁
文件大?。?/td> 470K
代理商： NJU6677CL
NJU6677
The NJU6677 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the
instruction and execution performs depending on the internal timing only neither the external clock. In case of
serial interface, the data input as MSB first serially.
The Table. 4 shows the instruction codes of the NJU6677.
Table 4. Instruction Code
Instructio n
C o d e
D e s c rip tion
A 0
R D
W -
R
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
(1 )
D isp la y O N /O F F
0
1
0
1
0
1
0
1
1
1
0
1
L C D D ispla y O N /O F F
0 :O F F 1 :O N
(2 )
D isp la y S ta rt L ine S e t
H igh O rd e r 4 b its
0
1
0
0
1
0
1
H igh O rd e r
A d d ress
D e te rm ine the D ispla y Line of
R A M to the C O M 0 .
(S e t the H igher order 4bits)
D isp la y S ta rt L ine S e t
L o w e r Order 4bits
0
1
0
0
1
1
0
L o w e r Order
A d d ress
D e te rm ine the D ispla y Line of
R A M to the C O M 0 .
(S e t the L o w e r order 4bits )
(3 )
P a g e A d d re s s S e t
4 b its
0
1
0
1
1
0
0
P a g e A d d ress
S e t th e 4 b it p a g e o f D D R A M
to the P a g e A d d re s s R e g iste r
(4 )
C o lum n A d d re s s S e t
H igh O rd e r 4 b its
0
1
0
0
0
0
1
H igh O rd e r
C o lum n A d d
.
S e t the Higher o rd e r 4 bits
C o lum n A d d re s s to the R e g .
C o lum n A d d re s s S e t
L o w e r Order 4bits
0
1
0
0
0
0
0
L o w e r Order
C o lum n A d d .
S e t th e L o w e r order 4 bits
C o lum n A d d re s s to the R e g .
(5 )
S ta tus R e a d
0
0
1
S ta tus
0
0
0
0
R e a d o ut the inte rna l S ta tus
(6 )
W rite D ispla y D a ta
1
1
0
W rite D a ta
W rite the d a ta into the D isp la y
D a ta R A M
(7 )
R e a d D isp la y D a ta
1
0
1
R e a d D a ta
R e a d the d a ta fro m the D isp la y
D a ta R A M
(8 )
N o rm a l o r Inve rse o f
O N /O F F S e t
0
1
0
1
0
1
0
0
1
1
0
1
Inve rse the O N a n d O F F
D isp la y
0 :N o rm a l 1 :Inve rse
(9 )
W hole D isp la y O N
/N o rm a l D isp la y
0
1
0
1
0
1
0
0
1
0
0
1
W hole D isp la y Turns O N
0 :N o rm a l 1 :W hole D isp. O N
(1 0 )
S ub instruc tion ta b le
m o d e
0
1
0
0
1
1
1
0
0
0
0
S e t the S ub instruc tion table .
(11 )
P a rtia l D ispla y
1 s t B lo c k , S e t
S ta rt d ispla y unit
0
1
0
0
0
0
0
S ta rt d ispla y
unit
S e t the S ta rt d isp la y unit o f 1st
B lo c k .
1 s t B lo c k ,
S e t The num b e r o f
d isp la y units
0
1
0
0
0
0
1
num b e r o f
d isp la y units
S e t the num b e r o f d isp la y units
o f 1 s t B lock.
2 n d B lo c k , S e t
S ta rt d ispla y unit
0
1
0
0
0
1
0
S ta rt d ispla y
unit
S e t the S ta rt d isp la y unit o f 2nd
B lo c k .
2 n d B lo c k ,
S e t The num b e r o f
d isp la y units
0
1
0
0
0
1
1
num b e r o f
d isp la y units
S e t the num b e r o f d isp la y units
o f 2nd B lock.
P a rtia l d isp la y o n
0
1
0
0
1
0
0
0
0
0
0
It c o m e s o ff the m o d e to s e t
a n d a d ispla y is e xecute d .
(1 2 )
n-line Inve rse D rive
S e t
R e g iste r S e t
H igher order 2 bits
0
1
0
0
1
0
1
*
*
higher
o rd e r
S e t the num b e r o f inve rse d rive
line .
R e g iste r S e t
L o w e r o rd e r 4 bits
0
1
0
0
1
1
0
L o w e r o rd e r
S e t the num b e r o f inve rse d rive
line .
n-line Inve rse D rive
S e t is e xecute d .
0
1
0
0
1
1
1
0
0
0
0
The e xe c ution of the line inve rse
d rive .
(1 3 )
E V R R e g iste r S e t
E V R R e g iste r S e t
H igher order 4 bits
0
1
0
1
0
0
0
E V R D a ta
H igher order
S e t the V
5
output level to the
E V R re g iste r. (H igher order 4
b its )
E V R R e g iste r S e t
L o w e r o rd e r 4 bits
0
1
0
1
0
0
1
E V R D a ta
L o w e r o rd e r
S e t the V
5
output level to the
E V R re g iste r. (L o w e r order 4
b its )
E V R R e g iste r S e t
is e xe c ute d .
0
1
0
1
0
1
0
0
0
0
0
The e xe c ution of the E V R .
(1 4 )
E nd of sub instructio n
ta b le m o d e
0
1
0
0
1
1
1
0
0
0
1
It ends the s e tting o f sub
ins truction ta b le .
(*:Don't Care)
(2) Instruction
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