
PART NUMBER
PACKAGE OUTLINE
PARAMETERS AND CONDITIONS
NE71300
00 (CHIP)
SYMBOLS
NF
OPT1
UNITS
MIN
TYP
MAX
Optimum Noise Figure, V
DS
= 3 V, I
DS
= 10 mA,
f = 4 GHz
f = 12 GHz
Associated Gain, V
DS
= 3 V, I
DS
= 10 mA,
f = 4 GHz
f = 12 GHz
dB
dB
0.6
1.6
0.7
1.8
G
A1
dB
dB
11.5
8.5
14.0
9.5
P
1dB
Output Power at 1 dB Compression, V
DS
= 3 V, I
D
s = 30 mA,
f =12 GHz
dBm
14.5
I
DSS
Saturated Drain Current, V
DS
= 3 V, V
GS
= 0
mA
20
40
120
V
P
Pinch-Off Voltage, V
DS
= 3 V, I
DS
= 0.1 mA
V
-3.5
-1.1
-0.5
g
m
Transconductance, V
DS
= 3 V, I
DS
= 10 mA
mS
μ
A
°
C/W
20
50
I
GSO
Gate to Source Leakage Current at V
GS
= -5 V
1.0
10
R
TH (CH-C)2
Thermal Resistance (Channel to Case)
190
FEATURES
LOW NOISE FIGURE
NF = 1.6 dB TYP at f = 12 GHz
HIGH ASSOCIATED GAIN
G
A
= 9.5 dB TYP at f = 12 GHz
L
G
= 0.3
μ
m, W
G
= 280
μ
m
EPITAXIAL TECHNOLOGY
LOW PHASE NOISE
LOW NOISE
L TO K-BAND GaAs MESFET
NE71300
N
A
A
NOISE FIGURE & ASSOCIATED GAIN
vs. FREQUENCY
V
DS
= 3 V, I
DS
= 10 mA
Frequency, f (GHz)
DESCRIPTION
The NE71300 features a low noise figure and high associ-
ated gain through K-band by employing a recessed 0.3 micron
gate and triple epitaxial technology. The active area of the
chip is covered with Si0
2
and Si
3
N
4
for scratch protection as
well as surface stability. This device is suitable for both
amplifier and oscillator applications in the consumer and
industrial markets.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
California Eastern Laboratories
ELECTRICAL CHARACTERISTICS
(T
A
= 25
°
C)
Notes:
1. RF performance is determined by packaging and testing 10 samples per wafer; wafer rejection criteria for standard devices is 2 rejects for 10
samples.
2. Chip mounted on infinite heat sink.
1
2
10
20
30
6
9
12
15
18
21
24
0
0.5
1
1.5
2
2.5
3
NF
G
A