參數(shù)資料
型號(hào)： NCV7361AD
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 通用總線功能
英文描述： Voltage Regulator with Integrated LIN Transceiver
中文描述： LINE TRANSCEIVER, PDSO8
封裝： SOIC-8
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 192K
代理商： NCV7361AD
NCV7361A
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS
(7.0 V
V
SUP
18 V, 40
°
C
T
A
125
°
C unless otherwise noted)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
RESET AC CHARACTERISTICS
Reset Time
t
Res
5.25
V
SUP
18 V
70
100
140
ms
Reset Rise Time (Note 9)
t
rr
5.25
V
SUP
18 V
3.0
7.5
15
s
BUS Debounce Time (Note 14)
t
deb_BUS
1.5
2.8
4.0
s
WakeUp Time
t
Wake_BUS
25
60
120
s
GENERAL LIN BUS INTERFACE AC CHARACTERISTICS
Transmit Propagation Delay
TxD > BUS (Notes 10 and 11)
t
dr_TxD
,
t
df_TxD
R
/C
at BUS
1.0 k /1.0 nF
660 /6.8 nF
500 /10 nF
4.0
s
Symmetry of Propagation Delay
BUS > RxD (Note 10)
t
dsym_TxD
t
dr_TxD
t
df_TxD
2.0
2.0
s
Receiver Propagation Delay
BUS > RxD (Notes 10 and 11)
t
dr_RxD
t
df_RxD
C
L(RxD)
= 50 pF
6.0
s
Symmetry of Propagation Delay
TxD > BUS (Note 10)
t
dsym_RxD
t
dr_RxD
t
df_RxD
2.0
2.0
s
Slew Rate BUS Rising Edge (Note 9)
dV/dT
rise
20%
C
L
= 1.0 nF, R
L
= 1.0 k
V
BUS
80%
1.0
1.7
2.5
V/ s
Slew Rate BUS Falling Edge (Note 9)
dV/dT
fall
20%
C
L
= 1.0 nF, R
L
= 1.0 k
V
BUS
80%
2.5
1.7
1.0
V/ s
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 1.3
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
t
sdom
V
= 8.0 V
R
L
= 500 /C
L
= 10 nF
12
s
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
t
srec
V
SUP
= 8.0 V
R
L
= 500 /C
L
= 10 nF
12
s
Slope Time Symmetry
t
ssym
V
= 8.0 V
R
L
= 500 /C
L
= 10 nF
T
ssym
= t
sdom
t
srec
7.0
1.0
s
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
t
sdom
V
= 18 V
R
L
= 500 /C
L
= 10 nF
18
s
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
t
srec
V
SUP
= 18 V
R
L
= 500 /C
L
= 10 nF
18
s
Slope Time Symmetry
t
ssym
V
SUP
= 18 V
R
L
= 500 /C
L
= 10 nF
T
ssym
= t
sdom
t
srec
5.0
5.0
s
9. Not production tested, guaranteed by design and qualification.
10.See Figures 2 and 3, Timing Diagrams.
11.See Figures 5, 6, 7, 8, and 9 for test setup.
12.t
sdom
= (t
VBUS40%
t
VBUS95%
) / 0.55.
13.t
sdom
= (t
VBUS60%
t
VBUS5%
) / 0.55.
14.See Figure 18.
ELECTRICAL CHARACTERISTICS
( V
SUP
= 7.0 V to 18 V; BUS loads: 1.0 k
/ 1 nF; 660
/ 6.8 nF; 500
/ 10 nF, T
xD
Signal:
t
Bit
= 50 s, t
wH
= T
wL
= t
Bit
; t
rise
= t
fall
< 100 ns, 40
°
C = T
A
= 125
°
C unless otherwise noted)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 2.0
Minimal Recessive Bit Time (Notes 15 and 16)
t
rec(min)
40
50
58
s
Maximum Recessive Bit Time (Notes 15 and 16)
t
rec(max)
40
50
58
s
Duty Cycle 1
D
1
D
1
= t
rec(min)
/ (2 * t
Bit
)
0.396
Duty Cycle 2
D
2
D
2
= t
rec(max)
/ (2 * t
Bit
)
0.581
15.See Timing Diagrams.
16.See Test Circuits for Dynamic and Static Characteristics.
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