參數(shù)資料
型號: NCV7361AD
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Voltage Regulator with Integrated LIN Transceiver
中文描述: LINE TRANSCEIVER, PDSO8
封裝: SOIC-8
文件頁數(shù): 19/28頁
文件大小: 192K
代理商: NCV7361AD
NCV7361A
http://onsemi.com
19
MIN/MAX SLOPE TIME CALCULATION
Figure 27. Slope Time Calculation
95%
100%
0%
t
srec
t
sdom
V
BUS
40%
V
dom
60%
5%
BUS
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dV dt
0.2 *Vswing(t40%t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope
5 * (t40%t60%)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope
VswingdV dt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because
it’s a passive edge. In case of low battery voltages and high
bus loads the rising edge is only determined by the network.
If the rising edge slew rate exceeds the value of the
dominant one, the slew rate control determines the rising
edge.
Power Dissipation and Operating Range
The max power dissipation depends on the thermal
resistance of the package and the PCB, the temperature
difference between Junction and Ambient as well as the
airflow.
The power dissipation can be calculated with:
PD
(VSUP
VOUT) * IVOUT
The power dissipation of the transmitter P
D_TX
depends
on the transceiver configuration and its parameters as well
as on the bus voltage V
BUS
= V
BAT
V
D
, the resulting
termination resistance R
L
, the capacitive bus load C
L
and
the bit rate. Figure 28 shows the dependence of power
dissipation of the transmitter as function of V
SUP
. The
conditions for calculation the power dissipation was:
R
L
= 500 , C
L
= 10 nF, Bitrate = 20 kbit and duty cycle
on TxD of 50%.
PD_TX
Figure 28. Power Dissipation LIN Transceiver
@ 20 kbit
5
50
17
40
18
15
14
V
SUP
(V)
P
D
30
10
0
6
16
19
7
20
45
35
25
5
15
13
12
11
10
8
9
The permitted package power dissipation can be
calculated:
PDmax
TJ
RJA
TA
If we consider that P
D_TX_max
= f(V
SUP
), it can be
calculated the max output current IV
OUT
on V
OUT
:
IVOUTmax
TJTA
RJA
PD_TX_max@ VSUP
VSUP
VOUT
T
J
T
A
is the temperature difference between junction
and ambient, and R
th
is the thermal resistance of the
package. The thermal energy is transferred via the package
and the pins to the ambient. This transfer can be improved
with additional ground areas on the PCB as well as ground
areas under the IC.
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