參數(shù)資料
型號: NCV7361AD
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Voltage Regulator with Integrated LIN Transceiver
中文描述: LINE TRANSCEIVER, PDSO8
封裝: SOIC-8
文件頁數(shù): 14/28頁
文件大?。?/td> 192K
代理商: NCV7361AD
NCV7361A
http://onsemi.com
14
Figure 18. Receive Mode Impulse Diagram
60%
t < t
deb_BUS
V
SUP
RxD
40%
BUS
50%
V
thr_max
V
thr_min
V
thr_hys
V
thr_cnt
t < t
deb_BUS
The receive threshold values V
thr_max
and V
thr_min
are
symmetrical to 0.5*V
SUP
with a hysteresis of 0.135*V
SUP
.
The LIN specific receive threshold is between 0.4*V
SUP
and 0.6 * V
SUP
.
Data Rate
The NCV7361A is a
constant slew rate
transceiver. The
bus driver works with a fixed slew rate range of 1.0 V/ s
V/ T
2.5 V/ s. This principle provides good
symmetry of the slope times between recessive to dominant
and dominant to recessive slopes within the LIN bus load
range (C
BUS
, R
term
).
The NCV7361A guarantees data rates up to 20 kb within
the complete bus load range under worst case conditions.
The constant slew rate principle holds appropriate voltage
levels and can operate within the LIN Protocol
Specification for RC oscillator systems with a matching
tolerance up to
2% between 2 nodes.
TxD Input
The 5.0 V input TxD directly controls the BUS level:
TxD = low
BUS = low (dominant level)
TxD = high
BUS = high (recessive level)
The TxD pin has an internal pullup resistor connected to
V
OUT
. This guarantees that an open TxD pin generates a
recessive BUS level.
Figure 19. TxD Input Circuitry
RC Filter
(10 ns)
Typ.
15 k
NCV7361A
MCU
TxD
R
PU_TxD
I
PU_TxD
V
CC
V
OUT
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