參數(shù)資料
型號: NCP5322ADWR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC
中文描述: 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28
封裝: LEAD FREE, SOIC-28
文件頁數(shù): 23/31頁
文件大?。?/td> 726K
代理商: NCP5322ADWR2G
NCP5322A
http://onsemi.com
23
voltage increase at the V
DRP
pin at fullload ( V
DRP
), the
designer must consider the output inductor’s resistance
(R
L
), the PCB trace resistance between the current sense
points (R
PCB
), and the controller IC’s gain from the current
sense to the V
DRP
pin (G
VDRP
):
VDRP
IO,MAX
(RL
RPCB)
GVDRP
(30)
The value of R
DRP
can then be calculated:
RDRP
VDRP
(IBIASVFB
VOUT,FULLLOADRFBK1)
(31)
V
OUT,FULLLOAD
is the fullload voltage reduction
from the VID (DAC) setting. V
OUT,FULLLOAD
is
not
the
voltage change from the noload AVP setting.
7. Current Sensing
For inductive current sensing, choose the current sense
network (R
CSn
, C
CSn
, n = 1 or 2) to satisfy
RCSn
CCSn
Lo (RL
RPCB)
(32)
+
+
G
VDRP
Σ
R
CS1
CS1
C
CS1
L1
I
MAX
/2
+
G
VDRP
R
CS2
CS2
C
CS2
L2
I
MAX
/2
CS
REF
COMP
Error
Amp
VID Setting
IBIAS
VFB
R
DRP
R
VFBK
V
DRP
= VID +
I
MAX
R
L
G
VDRP
V
FB
= VID
V
CORE
I
DRP
I
FBK
V
CORE
= VID (I
DRP
IBIAS
VFB
) R
VFBK
= VID I
MAX
R
L
G
VDRP
R
FBK
/R
DRP
+ IBIAS
VFB
R
FBK
Figure 19. AVP Circuitry at FullLoad
I
DRP
= I
MAX
R
L
G
VDRP
/R
DRP
I
FBK
= I
DRP
IBIAS
VFB
+
Figure 20. V
DRP
Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Long
(Slow): V
DRP
and V
OUT
Respond Too Slowly.
Figure 21. V
DRP
Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Short
(Fast): V
DRP
and V
OUT
Both Overshoot.
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