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NCP5322A
http://onsemi.com
22
where;
T
is the total thermal impedance (
JC
+
SA
).
JC
is the junctiontocase thermal impedance of the
MOSFET.
SA
is the sinktoambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used).
T
J
is the specified maximum allowed junction
temperature.
T
A
is the worst case ambient operating temperature.
For TO220 and TO263 packages, standard FR4
copper clad circuit boards will have approximate thermal
resistances (
SA
) as shown below:
Pad Size
(in
2
/mm
2
)
SingleSided
1 oz. Copper
0.5/323
6065
°
C/W
0.75/484
5560
°
C/W
1.0/645
5055
°
C/W
1.5/968
4550
°
C/W
2.0/1290
3842
°
C/W
2.5/1612
3337
°
C/W
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading, and component
variations (i.e. worst case MOSFET R
DS(on)
). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, its advisable to have as
much heatsink area as possible – all too often new designs
are found to be too hot and require redesign to add
heatsinking.
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
Voltage Positioning: R
FBK1
and R
DRP
. R
FBK1
establishes the
noload “high” voltage position and R
DRP
determines the
fullload “droop” voltage.
Resistor R
FBK1
is connected between V
CORE
and the V
FB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V
FB
pin and develop a voltage
drop from V
CORE
to the V
FB
pin. Because the error amplifier
regulates V
FB
to the DAC setting, the output voltage,
V
CORE
, will be higher by the amount IBIAS
VFB
R
FBK1
.
This condition is shown in Figure 18.
To calculate R
FBK1
the designer must specify the noload
voltage increase above the VID setting ( V
NOLOAD
) and
determine the V
FB
bias current. Usually, the noload voltage
increase is specified in the design guide for the processor
that is available from the manufacturer. The V
FB
bias current
is determined by the value of the resistor from R
OSC
to
ground (see Figure 5 in the data sheet for a graph of
IBIAS
VFB
versus R
OSC
). The value of R
FBK1
can then be
calculated:
+
+
G
VDRP
Σ
R
CS1
CS1
C
CS1
L1
0 A
+
G
VDRP
R
CS2
CS2
C
CS2
L2
0 A
CS
REF
COMP
Error
Amp
VID Setting
IBIAS
VFB
R
DRP
R
VFBK
V
DRP
= VID
V
FB
= VID
V
CORE
I
DRP
= 0
I
FBK
= IBIAS
VFB
V
CORE
= VID + IBIAS
VFB
R
VFBk
Figure 18. AVP Circuitry at NoLoad
+
RFBK1
VNOLOADIBIASVFB
(29)
Resistor R
DRP
is connected between the V
DRP
and the
V
FB
pins. At noload, the V
DRP
and the V
FB
pins will both
be at the DAC voltage so this resistor will conduct zero
current. However, at fullload, the voltage at the V
DRP
pin
will increase proportional to the output inductor’s current
while V
FB
will still be regulated to the DAC voltage. Current
will be conducted from V
DRP
to V
FB
by R
DRP
. This current
will be large enough to supply the V
FB
bias current and cause
a voltage drop from V
FB
to Vcore across R
FBK
– the
converter’s output voltage will be reduced. This condition is
shown in Figure 19.
To determine the value of R
DRP
the designer must specify
the fullload voltage reduction
from the VID
(DAC) setting
( V
OUT,FULLLOAD
) and predict the voltage increase at the
V
DRP
pin at fullload. Usually, the fullload voltage
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the