參數(shù)資料
型號(hào)： NCP5314FTR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Two/Three/Four−Phase Buck CPU Controller
中文描述： SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQFP32
封裝： LEAD FREE, LQFP-32
文件頁數(shù)： 22/29頁
文件大小： 684K
代理商： NCP5314FTR2G
NCP5314
http://onsemi.com
22
I
RMS,CNTL
is the RMS value of the trapezoidal current in
the control MOSFET:
(20)
IRMS,CNTL
[(ILo,MAX2
D
ILo,MAX
ILo,MIN
ILo,MIN2) 3]1 2
I
Lo,MAX
is the maximum output inductor current:
ILo,MAX
IO,MAX
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX
I
O,MAX
is the maximum converter output current.
D is the duty cycle of the converter:
D
VOUTVIN
Δ
I
Lo
is the peaktopeak ripple current in the output
inductor of value L
o
:
ILo
(VIN
VOUT)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gatetosource charge plus the gatetodrain charge. This
may be specified in the data sheet or approximated from the
gatecharge curve as shown in the Figure 26.
ILo2
(21)
ILo2
(22)
(23)
D (Lo
fSW)
(24)
Qswitch
Qgs2
Qgd
(25)
I
g
is the output current from the gate driver IC.
V
IN
is the input voltage to the converter.
f
sw
is the switching frequency of the converter.
Q
G
is the MOSFET total gate charge to obtain R
DS(on)
;
commonly specified in the data sheet.
V
g
is the gate drive voltage.
Q
RR
is the reverse recovery charge of the
lower
MOSFET.
Q
oss
is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
(IRMS,SYNCH2
(Vfdiode
IO,MAX2
PD,SYNCH
RDS(on))
t_nonoverlap
fSW)
(26)
where:
Vf
diode
is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the nonoverlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate nonoverlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
(27)
IRMS,SYNCH
[(ILo,MAX2
1
D
ILo,MAX
ILo,MIN
ILo,MIN2) 3]1 2
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
(TJ
where:
θ
T
is the total thermal impedance (
θ
JC
+
θ
SA
);
θ
JC
is the junctiontocase thermal impedance of the
MOSFET;
θ
SA
is the sinktoambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
T
J
is the specified maximum allowed junction temperature;
T
A
is the worst case ambient operating temperature.
For TO220 and TO263 packages, standard FR4
copper clad circuit boards will have approximate thermal
resistances (
θ
SA
) as shown below:
T
TA) PD
(28)
Pad Size (in
2
/mm
2
)
SingleSided
1 oz Copper
0.50/323
6065
°
C/W
0.75/484
5560
°
C/W
1.00/645
5055
°
C/W
1.50/968
4550
°
C/W
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET R
DS(on)
). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require redesign to add heatsinking.
7. Adaptive Voltage Positioning
Two resistors program the Adaptive Voltage Positioning
(AVP): R
FB
and R
DRP
. These components form a resistor
divider, shown in Figures 27 and 28, between V
DRP
, V
FB
,
and V
OUT
.
Resistor R
FB
is connected between V
OUT
and the V
FB
pin
of the controller. At no load, this resistor will conduct the
very small internal bias current of the V
FB
pin. Therefore
V
FB
should be kept below 10 k
Ω
to avoid output voltage
error due to the input bias current. If the R
FB
resistor is kept
small, the V
FB
bias current can be ignored.
Resistor R
DRP
is connected between the V
DRP
and V
FB
pins of the controller. At no load, these pins should be at an
equal potential, and no current should flow through R
DRP
. In
reality, the bias current coming out of the V
DRP
pin is likely
to have a small positive voltage with respect to V
FB
. This
current produces a small decrease in output voltage at no
load, which can be minimized by keeping the R
DRP
resistor
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