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參數(shù)資料
| 型號： | NCP5314FTR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two/Three/Four−Phase Buck CPU Controller |
| 中文描述： | SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 684K |
| 代理商： | NCP5314FTR2G |
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NCP5314
http://onsemi.com
17
Since the internallyset thresholds for PWRLS are VID/2
for the lower threshold and VID + 80 mV for the upper
threshold, a simple equation can be provided to assist the
designer in selecting a resistor divider to provide the desired
PWRGD performance.
VLOWER
VVID
2
VVID
R1
R2
R1
VUPPER
80 mV
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 250
μ
s. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low.
In order to use the PWRGD pin as specified, the user is
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
PWRGD
low
ééé
ééé
V
LOWER
ééé
ééé
VID + 80 mV
V
OUT
HIGH
LOW
PWRGD
%
%
Figure 22. PWRGD Assertion Window
PWRGD
lo-
w
PWRGD
high
Figure 23. Adjusting the PWRGD Threshold
V
OUT
R1
R2
PWRLS
Undervoltage Lockout
The NCP5314 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until V
CC
applied to the IC reaches 9 V. The GATE outputs are disabled
when V
CC
drops below 8 V.
SoftStart
At initial powerup, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 40
μ
A. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Current Limit
Two levels of overcurrent protection are provided. First,
if the voltage between the Current Sense pins (CSxN and
CSxP) exceeds the fixed threshold (Single Pulse Current
Limit), the PWM comparator is turned off. This provides
fast peak current protection for individual phases. Second,
the individual phase currents are summed and externally
lowpass filtered to compare an averaged current signal to
a user adjustable voltage on the I
LIM
pin. If the I
LIM
voltage
is exceeded, the fault latch trips and the converter is latched
off. V
CC
must be recycled to reset the latch.
Fault Protection Logic
The NCP5314 includes fault protection circuitry to
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Gate Outputs
The NCP5314 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
The output voltage of the NCP5314 is set by means of a
6bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.5 k
Ω
pullup to a maximum of 3.3 V is
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high.
The output of the DAC is described in the Electrical
Characteristics section of the data sheet. These outputs are
consistent with VR10.x and processor specifications. The
DAC output is 20 mV below the VID code specification.
The latest VRM and processor specifications require a
power supply to turn its output off in the event of a 11111X
VID code. When the DAC sees such a code, the GATE pins
stop switching and go low. This condition is described in
Table 1.
Adjusting the Number of Phases
The NCP5314 was designed with a selectablephase
architecture. Designers may choose any number of phases
up to four. The phase delay is automatically adjusted to
match the number of phases that will be used. This feature
allows the designer to select the number of phases required
for a particular application.
Fourphase operation is standard. All phases switch with
a 90 degree delay between pulses. No special connections
are required.
Threephase operation is achieved by disabling phase 4.
Tie together CS4N and CS4P, and then pull both pins to V
CC
.
The remaining phases will continue to switch, but now there
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